Datasheet

ManualsBrandsAlliance Memory ManualsMemory ICsSRAM 8MB 55ns TSOP-II

FEATURES

Fast access time : 55ns

Low power consumption:

Operating current : 30mA (TYP.)

Standby current : 6µA (TYP.) LL-version

Single 2.7V ~ 5.5V power supply

All inputs and outputs TTL compatible

Fully static operation

Tri-state output

Data byte control : LB# (DQ0 ~ DQ7)

UB# (DQ8 ~ DQ15)

Data retention voltage : 1.5V (MIN.)

Lead free and green package available

Package : 44-pin 400 mil TSOP-II

48-ball 6mm x 8mm TFBGA

GENERAL DESCRIPTION

The AS6C8016 is a 8,388,608-bit low power

CMOS static random access memory organized as

524,288 words by 16 bits. It is fabricated using very

high performance, high reliability CMOS technology.

Its standby current is stable within the range of

operating temperature.

he AS6C8016 is well designed for low power

application, and particularly well suited for battery

back-up nonvolatile memory application.

The A

S6C8016 operates from a single power

supply of 2.7V ~ 5.5V and all inputs and outputs are

fully TTL compatible

PRODUCT FAMILY

Power Dissipation Product

Family

Operating

Temperature

Vcc Range Speed

Standby(I

SB1,TYP.) Operating(Icc,TYP.)

AS6C8016(I)

-40 ~ 85℃

2.7 ~ 5.5V 55ns 6µA(LL) 30mA

FUNCTIONAL BLOCK DIAGRAM

CONTROL

CIRCUIT

CE#

WE#

OE#

DECODER

512Kx16

MEMORY ARRAY

COLUMN I/O

A0-A18

Vcc

Vss

DQ8-DQ15

Upper Byte

DQ0-DQ7

Lower Byte

I/O DATA

CIRCUIT

LB#

UB#

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A18 Address Inputs

DQ0 – DQ15 Data Inputs/Outputs

CE# Chip Enable Input

WE# Write Enable Input

OE# Output Enable Input

LB# Lower Byte Control

UB# Upper Byte Control

Power Supply

Ground

512KX8 BIT LOW POWER CMOS SRAM

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 1 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM

Summary of content (12 pages)

PAGE 1
NOVEMBER 2007 January 2007 AS6C8016 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER FEATURES GENERAL DESCRIPTION Fast access time : 55ns Low power consumption: Operating current : 30mA (TYP.) Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.
PAGE 2
NOVEMBER 2007 January 2007 AS6C8016 X 8 BIT LOW POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER CMOS SRAM PIN CONFIGURATION A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# 5 40 UB# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 AS6C8016 A0 CE# A LB# OE# A0 A1 B DQ8 UB# A3 A4 CE# DQ0 DQ9 C DQ9 DQ10 A5 A6 DQ1 DQ2 D Vss DQ11 A17 A7 DQ3 Vcc E Vcc
PAGE 3
NOVEMBER 2007 January 2007 AS6C8016 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# OE# H X L L L L L L L L X X H H L L L X X X H = VIH, L = VIL, X = Don't care.
PAGE 4
NOVEMBER 2007 January 2007 AS6C8016 X 8 BIT LOW POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER CMOS SRAM AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.
PAGE 5
NOVEMBER 2007 January 2007 AS6C8016 X 8 BIT LOW POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.
PAGE 6
NOVEMBER 2007 January 2007 AS6C8016 X 8 BIT LOW POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout T OW High-Z (4) (4) tDW tDH Data Valid Din WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din NOVEMBER/2007, V 1.0 tDH Data Valid Alliance Memory Inc.
PAGE 7
NOVEMBER 2007 January 2007 AS6C8016 X 8 BIT LOW POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER CMOS SRAM WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tCW tBW tAS LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.
PAGE 8
NOVEMBER 2007 January 2007 AS6C8016 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION _ VCC - 0.2V VCC for Data Retention VDR CE# > VCC = 1.5V _ VCC-0.2V Data Retention Current IDR CE# > Other pins at 0.2V or VCC-0.2V See Data Retention Chip Disable to Data tCDR Waveforms (below) Retention Time Recovery Time tR tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) MIN. 1.5 TYP. - MAX. 5.
PAGE 9
NOVEMBER 2007 January 2007 A S 6 C 8 0 1 6 X 8 BIT LOW POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION θ Ⅱ Package Outline Dimension 44-pin 400mil TSOP-Ⅱ SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0 NOVEMBER/2007, V 1.0 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.
PAGE 10
NOVEMBER 2007 January 2007 AS6C8016 X 8 BIT LOW POWER CMOS SRAM 512K X 16 BIT SUPER 512K LOW POWER CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension NOVEMBER/2007, V 1.0 Alliance Memory Inc.
PAGE 11
AS6C8016 NOVEMBER 2007 January 2007 X 8 BICMOS T LOW POWER 512K X 16 BIT SUPER 512K LOW POWER SRAM CMOS SRAM ORDERING INFORMATION Alliance Organization VCC Range Package Operating Temp Speed ns AS6C8016 -55ZIN 512K x 16 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 C - 85 C 55 AS6C8016 -55BIN 512K x 16 2.7 - 5.5V 48ball TBGA Industrial ~ -40 C - 85 C 55 PART NUMBERING SYSTEM AS6C 8016 -55 Device Number low power SRAM prefix 80 = 8M 16 = x16 NOVEMBER/2007, V 1.
PAGE 12
NOVEMBER 2007 January 2007 AS6C8016 512K X 8CMOS BIT LOW 512K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM ® Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211 Copyright © Alliance Memory All Rights Reserved www.alliancememory.com © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance.