Datasheet

WRITE CYCLE 3
(LB#
,UB#
Controlled)
(1,2,5,6)
Dout
Din
Data Valid
tDW tDH
(4)
High-Z
tWHZ
WE#
LB#,UB#
t
CW
CE#
Address
tWR
tAS
tAW
tWC
tWP
tBW
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A
write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.Dur
ing a WE# controlled write cycl
e with OE# low, t
WP
must be greater than t
WHZ
+ t
DW
to allow the drivers to turn off and data to be
placed on the bus.
4.During
this period, I/O pins are in the output state, and input signals must not be applied.
5.I
f the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
st
ate.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
512K X 8 BIT LOW POWER CMOS SRAM
January 2007
NOVEMBER 2007
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 7 of 12
AS6C8016
512K X 16 BIT SUPER LOW POWER CMOS SRAM