Instruction manual

Configuration of the camera
12.4.14 Input/output pin control
All input and output signals running over the HiRose plug are controlled by this register.
Register Name Field Bit Description
0xF1000300 IO_INP_CTRL1 Pres dicates presence of ence_Inq [0] In
this feature (read
only)
--- [1..6]
Polarity [7] 0: low active, 1: high
active
[8..10] ---
InputMode [11..15] Mode
--- [16..30]
PinState [31] RD: Current state of
pin
0xF1000304 IO_INP e
IO_INP_CTRL1
_CTRL2 Sam as
Table 98: Input control configuration register
e Polarity flag determines whether the input is low active (0) or high active (1). The input
can be seen in the followin le used to query the current status of
the input.
For inputs, the PinState bit refers to the inverted output side of the optical coupler. This means
that an open input sets the PinState bit to “1”.
IO_INP_CTRL 1-2
Th
mode g tab . The PinState flag is
ID Mode
Default
0x00 Off
0x01 reserved
0x02 Trigger input Input 1
0x03 reserved
0x04 reserved
0x05 tbd (SPI external DCLK)
0x06..0x0F reserved
0x10..0x1F reserved
Table 99: Input routing
igger
more than one input is being o ted
AND.
Tr
If pera in trigger mode, these inputs are logically linked by
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