Instruction manual

Configuration of the camera
IO_OUTP_CTRL 1-2
ut and be queried and set
a the PinState flag.
The Polarity flag determines whether the output is low active (0) or high active (1). The output
mode can be seen in the following table. The current status of the outp
vi
Register Name Field Bit Description
0xF1000320 IO_OUTP_CTRL1 Presence_Inq [0] Indicates presence of
(read only) this feature
--- - [1..6]
Polarity [7] 0: low active, 1: high
active
--- [8..10]
Output mode Mode [11..15]
--- [16..30]
PinState [31] RD: Current state of pin
WR: New state of pin
0xF1000324 IO_OUTP_CTRL2 Same as
IO_OUTP_CTRL1
Table 100: Output control configuration register
Output mode
ID Mode Default
0x00 Off
0x01 Output state follows ‘PinState’ bit
0x02 Integration enable Output 1
0x03 reserved
0x04 tbd (SPI internal DCLK)
0x05 tbd (SPI external DCLK)
0x 6 FrameVal0 id
0x07 Busy
0x08 Follow corresponding input
(Inp1 → Out1, Inp2 → Out2, …)
Output 2
0x09..0x0F reserved
0x10..0x1F reserved
Table 101: Output ID
The “Polarity“ setting refers to the input side of the inverting optical coupler output, “PinState
0” switches off the output transistor and produces high level over the resistor.
12.4.15 Delayed Integration enable
A delay time between initiating exposure on the sensor and the activation edge of the IntEna
signal can be set using this register. The on/off flag activates/deactivates integration delay. The
time can be set in µs in DelayTime.
MARLIN Technical Manual
Page 166