Instruction manual
Table Of Contents
- Introduction
- Declarations of conformity
- Safety instructions
- PIKE types and highlights
- FireWire
- Overview
- FireWire in detail
- Serial bus
- FireWire connection capabilities
- Capabilities of 1394a (FireWire 400)
- Capabilities of 1394b (FireWire 800)
- Compatibility between 1394a and 1394b
- Image transfer via 1394a and 1394b
- 1394b bandwidths
- FireWire Plug & play capabilities
- FireWire hot plug precautions
- Operating system support
- 1394a/b comparison
- System components
- Specifications
- Camera dimensions
- PIKE standard housing (2 x 1394b copper)
- PIKE (1394b: 1 x GOF, 1 x copper)
- Tripod adapter
- Pike W90 (2 x 1394b copper)
- Pike W90 (1394b: 1 x GOF, 1 x copper)
- Pike W90 S90 (2 x 1394b copper)
- Pike W90 S90 (1394b: 1 x GOF, 1 x copper)
- Pike W270 (2 x 1394b copper)
- Pike W270 (1394b: 1 x GOF, 1 x copper)
- Pike W270 S90 (2 x 1394b copper)
- Pike W270 S90 (1394b: 1 x GOF, 1 x copper)
- Cross section: C-Mount (VGA size filter)
- Cross section: C-Mount (large filter)
- Adjustment of C-Mount
- F-Mount, K-Mount, M39-Mount
- Camera interfaces
- Description of the data path
- Block diagrams of the cameras
- Sensor
- Channel balance
- White balance
- Auto shutter
- Auto gain
- Manual gain
- Brightness (black level or offset)
- Horizontal mirror function
- Shading correction
- Look-up table (LUT) and gamma function
- Binning (b/w models)
- Sub-sampling
- High SNR mode (High Signal Noise Ratio)
- Frame memory and deferred image transport
- Color interpolation (BAYER demosaicing)
- Sharpness
- Hue and saturation
- Color correction
- Color conversion (RGB ‡ YUV)
- Bulk Trigger
- Level Trigger
- Serial interface
- Controlling image capture
- Video formats, modes and bandwidth
- How does bandwidth affect the frame rate?
- Configuration of the camera
- Camera_Status_Register
- Configuration ROM
- Implemented registers
- Camera initialize register
- Inquiry register for video format
- Inquiry register for video mode
- Inquiry register for video frame rate and base address
- Inquiry register for basic function
- Inquiry register for feature presence
- Inquiry register for feature elements
- Inquiry register for absolute value CSR offset address
- Status and control register for feature
- Feature control error status register
- Video mode control and status registers for Format_7
- Advanced features
- Version information inquiry
- Advanced feature inquiry
- Camera status
- Maximum resolution
- Time base
- Extended shutter
- Test images
- Look-up tables (LUT)
- Shading correction
- Deferred image transport
- Frame information
- Input/output pin control
- Delayed Integration enable
- Auto shutter control
- Auto gain control
- Autofunction AOI
- Color correction
- Trigger delay
- Mirror image
- AFE channel compensation (channel balance)
- Soft Reset
- High SNR mode (High Signal Noise Ratio)
- User profiles
- GPDATA_BUFFER
- Firmware update
- Glossary
- Index
Camera interfaces
PIKE Technical Manual V3.1.0
96
Pixel data
Pixel data are transmitted as isochronous data packets in accordance with
the 1394 interface described in IIDC V1.31. The first packet of a frame is
identified by the 1 in the sync bit (sy) of the packet header.
Note
L
• Note that trigger delay in fact delays the image cap-
ture whereas the IntEna_Delay only delays the leading
edge of the IntEna output signal but does not delay the
image capture.
• As mentioned before, it is possible to set the outputs
by software. Doing so, the achievable maximum fre-
quency is strongly dependent on individual software
capabilities. As a rule of thumb, the camera itself will
limit the toggle frequency to not more than 700 Hz.
Field Description
data_length Number of bytes in the data field
tg Tag field
shall be set to zero
channel Isochronous channel number, as programmed in the iso_channel
field of the cam_sta_ctrl register
tCode Transaction code
shall be set to the isochronous data block packet tCode
Table 41: Description of Data Block Packet Format
0-7 8-15 16-23 24-31
data_length tg channel tCode sy
header_CRC
Video data payload
data_CRC
Table 40: Isochronous data block packet format. Source: IIDC V1.31
sync bit