Cyclone III FPGA Development Kit User Guide Cyclone III FPGA Development Kit User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01027-1.
© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Contents Chapter 1. About This Kit Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv Contents 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 The SRAM&Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 SRAM . . . . . . . . . . . .
1. About This Kit Introduction Welcome to the Altera® Cyclone® III Development Kit, which includes a full-featured FPGA development board, hardware and software development tools, documentation, and accessories needed to begin FPGA development.
1–2 Chapter 1: About This Kit Documentation ■ MegaCore IP Library—This library contains Altera IP MegaCore functions.
2. Getting Started Introduction This user guide familiarizes you with the contents of the kit and guides you through the Cyclone III development board setup.
2–2 Chapter 2: Getting Started Before You Begin Inspect the Board Place the board on an anti-static surface and inspect it to ensure that it has not been damaged during shipment. c Without proper anti-static handling, the Cyclone III development board can be damaged. Verify that all components are on the board and appear intact. 1 In typical applications with the Cyclone III development board, a heatsink is not necessary.
Chapter 2: Getting Started References 2–3 References For other related information, refer to the following websites: Table 2–1. For More Information About Refer to Additional daughter cards available for purchase www.altera.com/products/devkits/kit-daughter_boards.jsp Cyclone III handbook www.altera.com/literature/lit-cyc3.jsp Cyclone III reference designs http://www.altera.com/products/devkits/altera/kit-cyc3.html eStore if you want to purchase devices www.altera.com/buy/devices/buy-devices.
2–4 Cyclone III FPGA Development Kit User Guide Chapter 2: Getting Started References September 2010 Altera Corporation
3. Software Installation Introduction This section describes the following procedures: 1 ■ “Installing the Cyclone III Development Kit” ■ “Installing the Quartus II Web Edition Software” on page 3–2 ■ “Installing the USB-Blaster Driver” on page 3–3 Before starting the installation, verify that you have complied with the conditions described in “Software Requirements” on page 2–2.
3–2 Chapter 3: Software Installation Installing the Quartus II Web Edition Software Table 3–1 lists the file directory names and a description of their contents. Table 3–1. Installed Directory Contents Directory Name Description of Contents board_design_files Contains schematic, layout, assembly, and bill of material board design files. Use these files as a starting point for a new prototype board design. demos Contains demonstration applications that may change from release to release.
Chapter 3: Software Installation Installing the USB-Blaster Driver ■ 3–3 MegaCore IP Library—A library that contains Altera IP MegaCore functions.
3–4 Cyclone III FPGA Development Kit User Guide Chapter 3: Software Installation Installing the USB-Blaster Driver September 2010 Altera Corporation
4. Development Board Setup Introduction The instructions in this chapter explain how to install the development board and configure the FPGA. Requirements Before starting the installation, verify that you have complied with the conditions described in “Hardware Requirements” on page 2–2 and have completed the following requirements: 1 September 2010 ■ Quartus II software installed on the host computer ■ USB-Blaster driver software installed on the host computer.
4–2 Chapter 4: Development Board Setup Powering Up the Board Powering Up the Board Figure 4–1 shows the Cyclone III development board and its components. Figure 4–1.
Chapter 4: Development Board Setup Powering Up the Board 4–3 Table 4–1. Switch SW1 Settings (Part 2 of 2) Function Switch Position 0 3 Default Position Name RSV0 Position 1 MAX_RESERVE0 X MAX_RESERVE1 X 4 RSV1 5 MAX0 6 MAX1 MAX_DIP1 X 7 MAX2 MAX_DIP2 X 8 MAX3 MAX_DIP3 X PFL Disable PFL Enable 1 Note to Table 4–1: (1) X = don’t care 4. Ensure that the 4-position SW3 mini-DIP switches and the two jumpers are set to the default positions shown in Table 4–2. Table 4–2.
4–4 Chapter 4: Development Board Setup Configuring the FPGA Configuring the FPGA Before configuring the FPGA, ensure that the Quartus II software and the USB-Blaster driver software are installed on the host computer and the development board is powered on. f For USB-Blaster driver installation information, refer to “Installing the USB-Blaster Driver” on page 3–3. To configure the Cyclone III FPGA, perform the following steps: 1.
5. Board Update Portal Introduction The Cyclone III FPGA Development Kit ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board. The design consists of a Nios II embedded processor, an Ethernet MAC, and an HTML web server. When you power up the board with the PGM CONFIG SELECT rotary switch (SW5) in position 0, the Cyclone III FPGA configures with the Board Update Portal design example.
5–2 Chapter 5: Board Update Portal Using the Board Update Portal to Update User Designs 5. Click Cyclone III FPGA Development Kit on the Board Update Portal web page to access the kit’s home page. Visit this page occasionally for documentation updates and additional new designs. f You can also navigate directly to the Cyclone III FPGA Development Kit page of the Altera website to determine if you have the latest kit software.
6. Board Test System Introduction The kit includes a design example and application called the Board Test System to test the functionality of the Cyclone III FPGA development board. The application provides an easy-to-use interface to alter functional settings and observe the results. You can use the application to test board components, modify functional parameters, observe performance, and measure power usage. The application is also useful as a reference for designing systems.
6–2 Chapter 6: Board Test System Preparing the Board A GUI runs on the PC which communicates over the JTAG bus to a test design running in the Cyclone III device. Figure 6–1 shows the initial GUI for a board that is in the factory configuration. Figure 6–1. Board Test System Graphical User Interface Several designs are provided to test the major board features. Each design provides data for one or more tabs in the application.
Chapter 6: Board Test System Running the Board Test System 6–3 3. Set the PGM CONFIG SELECT rotary switch (SW5) to position 1. 4. Turn the power to the board on. The board loads the design stored in the user hardware 1 portion of flash memory into the FPGA. If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal, the design that loads tests accessing the GPIO, SRAM, and flash memory.
6–4 Chapter 6: Board Test System Using the Board Test System Using the Board Test System This section describes each control in the Board Test System application. The Configure Menu Each test design tests different functionality and corresponds to one or more application tabs. Use the Configure menu to select the design you want to use. Figure 6–2 shows the Configure menu. Figure 6–2. The Configure Menu 1.
Chapter 6: Board Test System Using the Board Test System 1 6–5 Connecting a jumper shunt on J6 and an external USB-Blaster on J14 includes the MAX II device in the JTAG chain. Board Information The Board information controls display static information about your board. Flash Memory Map The Flash memory map control shows the memory map of the flash memory device on your board. The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I/O components on your board.
6–6 Chapter 6: Board Test System Using the Board Test System The following sections describe the controls on the GPIO tab. Character LCD The Character LCD controls allow you to display text strings on the character LCD on your board. Type text in the text boxes and then click Write. 1 If you exceed the 16 character display limit on either line, a warning message appears.
Chapter 6: Board Test System Using the Board Test System 6–7 The SRAM&Flash Tab The SRAM&Flash tab allows you to read and write SRAM and flash memory on your board. Figure 6–4 shows the SRAM&Flash tab. Figure 6–4. The SRAM&Flash Tab The following sections describe the controls on the SRAM&Flash tab. SRAM The SRAM control allows you to read and write the SRAM on your board. Type a starting address in the text box and click Read. Values starting at the specified address appear in the top row of the table.
6–8 Chapter 6: Board Test System Using the Board Test System To update the SRAM contents, change values in the table and click Write. The application writes the new values to SRAM and then reads the values back to guarantee that the graphical display accurately reflects the memory contents. Flash The Flash control allows you to read and write the flash memory on your board. Type a starting address in the text box and click Read. Values starting at the specified address appear in the top row of the table.
Chapter 6: Board Test System Using the Board Test System 6–9 The Graphic LCD Tab The Graphic LCD tab allows you to write to the LCD on your board. Figure 6–3 shows the Graphic LCD tab. Figure 6–5. The Graphic LCD Tab The following section describes the controls on the Graphic LCD tab. Graphics LCD The Graphics LCD controls allow you to display Bitmap Image File (.bmp) on the graphic LCD on your board: 1 September 2010 ■ Select File—opens the browser window to allow you to select a .
6–10 Chapter 6: Board Test System Using the Board Test System The DDR2 Tab The DDR2 tab allows you to read and write to one of two DDR2 memory ports on your board. The DDR2 memory configuration is divided into top design (implemented by DDR2 chip U11, U12, U13) and bottom design (implemented by DDR2 chip U25, U26). Figure 6–6 shows the DDR2 tab when the board is configured with DDR2 top design. Figure 6–6. The DDR2 Tab The following sections describe the controls on the DDR2 tab.
Chapter 6: Board Test System Using the Board Test System 6–11 Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start: ■ Write, Read, and Total performance bars—show the percentage of maximum theoretical data rate that the requested transactions are able to achieve. ■ Write(MBps), Read(MBps), and Total(MBps)—show the number of bytes of data analyzed per second.
6–12 Cyclone III FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System September 2010 Altera Corporation
7. Power Measurement Introduction One of the main features of the Cyclone III FPGA device is its low power consumption. You can measure the power used by the 3C120 FPGA device on the Cyclone III development board for various conditions with a power design example provided with the kit. With the power design example you can control the amount of logic utilized in the FPGA, the clock frequency, and the number of I/Os used, and measure the effect on power used by the Cyclone III device.
7–2 Chapter 7: Power Measurement Power Design Example The LEDs in Table 7–2 indicate the power-state values of the design example as User_PB1 advances frequency. Table 7–2. Power State Indicators for Frequency LED1 (AE20) LED0 (AD15) Frequency (MHz) 0 0 0 0 1 33 1 0 67 1 1 100 The LEDs in Table 7–3 indicate the power-state values of the design example (and number of output pins, when enabled by User_PB3) as User_PB2 advances resource utilization. Table 7–3.
Chapter 7: Power Measurement Measuring Power 7–3 Measuring Power You can measure power by using the analog-to-digital (A/D) circuitry on the development board or by using a digital multi-meter (DMM) across on-board sense resistors. However, note that, depending on the DMM accuracy, the on-board A/D measurements tend to produce considerably more accurate results.
7–4 Chapter 7: Power Measurement Measuring Power 2. Download the cycloneIII_dev_powerdemo.sof file as described in “Configuring the FPGA” on page 4–4. The power design example is in \...\examples\cycloneIII_3c120_dev_powerdemo. 3. Set the POWER SELECT rotary switch SW4 to 5. 4. Observe the 4-digit hexadecimal display for the I/O output power in watts on banks 1 and 2. 5.
Chapter 7: Power Measurement Changing the Design Example 7–5 Calculating Power To obtain the power P in watts, measure the voltage across the sense resistors, VSENSE, and calculate the nominal power as follows: If VSENSE = Voltage measured across the sense resistor ISENSE = Current through the sense resistor VSUPPLY = FPGA supply voltage RSENSE = Sense resistor value in Table 7–5. then Equation 7–1.
7–6 Cyclone III FPGA Development Kit User Guide Chapter 7: Power Measurement Changing the Design Example September 2010 Altera Corporation
8. Design Tutorials Introduction The example designs and tutorials included in the Cyclone III Development Kit help familiarize new users with development board features. My First FPGA Design Tutorial and My First Nios II Software Tutorial provide step-by-step guidance for the first-time user. My First FPGA Tutorial My First FPGA Design Tutorial describes how to create a simple Altera FPGA design.
8–2 Cyclone III FPGA Development Kit User Guide Chapter 8: Design Tutorials My First Nios II Software Tutorial September 2010 Altera Corporation
A. Programming the Flash Device Overview There is a Common Flash Interface (CFI) type flash memory device on the Cyclone III development board. When you first receive the kit, this CFI flash device arrives programmed with a default factory configuration that was loaded from a Programmer Object File (.pof). When you power up the board, the CFI flash device configures the FPGA with the default factory configuration using Passive Serial (PS) programming.
A–2 Appendix A: Programming the Flash Device Creating a Flash File 3. Click Options. In the Options dialog box, enter 0x3FE0000 and click OK. This sets the option bit base address for the development kit to the required default, 0x3FE0000. The option bit sector stores the start address for each page of memory and also stores the Page Valid bits. The Page Valid bits indicate whether each page is successfully programmed.
Appendix A: Programming the Flash Device Creating a Flash File 1 A–3 If you choose to overwrite an existing .pof file, you receive a warning message. Figure A–1. Convert Programming Files Settings 6. Click Generate. Generation takes a short time and it is confirmed by a “Generated… pof successfully” message. You now have a successfully generated .pof that can be programmed to the flash device to automatically configure the FPGA on your Cyclone III development board.
A–4 Appendix A: Programming the Flash Device Parallel Flash Loader Instantiation Parallel Flash Loader Instantiation The development kit includes a PFL megafunction design, cycloneIII_3c120_dev_pfl, in the directory \...\examples. The Quartus II software uses the PFL to write programming files to the flash device, which then loads the FPGA on power up.
Appendix A: Programming the Flash Device Programming the Flash Device A–5 8. Click Start to download the selected configuration file to the FPGA (Figure A–2). The FPGA is configured when the progress bar reaches 100%, after which it is ready to access and program the flash device. Figure A–2. PFL Programming 9. Click Auto Detect. The EP3C120 device and a child CFI_512MB device appear in the list of devices to be programmed. 10. Double-click the field of the CFI_512MB row.
A–6 Appendix A: Programming the Flash Device Restoring the Factory Design to the Flash Device 11. Turn on Page_0 and OPTION_BITS options in the Program/Configure column that correspond to the CFI_512MB device (Figure A–3). This results in writes only to the flash page zero and the option bit register. Figure A–3. Program/Configure Options 12. Click Start. The message window details the flash writing progress to successful completion.
Additional Information This chapter provides additional information about the document and Altera. Document Revision History The following table shows the revision history for this document. Date Version September 2010 July 2010 March 2009 August 2008 October 2007 1.4 1.3 1.2 1.1 1.0 Changes ■ Added Chapter 5, Board Update Portal and Chapter 6, Board Test System. ■ Converted document to new frame template and made textual and style changes. ■ Updated Figure 3–1 on page 3–1.
Info–2 Additional Information Typographic Conventions Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.
