EECS 452 – Lecture 5 Today: FPGA / Cyclone II overview. The Altera DE2-70 board. Aspects of the Verilog/SystemVerilog HDLs Information relevant to lab exercise three. Yet more information. References: DE2-70 User Manual. DE2-70 demonstrations, V10. Altera Quartus II introductory course. Verilog in One Day Tutorial. Last one out should close the lab door!!!! Please keep the lab clean and organized. Design is where science and art break even.
Lecture overview ▶ FPGA overview. ▶ Altera Cyclone II overview. ▶ The Terasic/Altera DE2-70 board. ▶ Altera’s Quartus II design software. ▶ Various aspects of Verilog/SystemVerilog. ▶ Code examples. A significant part of learning is asking good questions. Or, in today’s world, using well chosen search terms. For example, verilog tutorial or verilog always block. The links included in today’s lecture note are some of the ones that I came across that I’ve found informative and useful.
Free eBook EECS 452 – Fall 2014 Lecture 5 – Page 3/143 Tuesday – September 16, 2014
Full Custom, ASIC, FPGA Full Custom: design at the transistor level. Application Specific Integrated Circuit: design using proved gate libraries. Starting chip likely already has transistors on it. Field Programmable Gate Arrary: interconnected configurable logic blocks. Ordered going down: decreasing cost, increasing ease to produce.
What is a Field Programmable Gate Array (FPGA)? From our viewpoint, (almost) unstructured logic that we can sculpt (configure) to meet our needs. In reality, a collection of small well defined logic blocks, a highly configurable interconnection network and a carefully designed clock distribution network. Plus whatever other features that a manufacturer might add to differentiate product. http://en.wikipedia.
FPGA organization Field Programmable Gate Array (reconfigurable logic) Not shown are off-fabric block RAM, multipliers, DSP blocks, PLL, etc. From rfneulink.com.
Routing makes all things possible ▶ First layers above gates/transistors form logic blocks or logic elements. ▶ The next layers support configuration of the blocks. ▶ The higher layers are programmable interconnects. ▶ Equal delays from to “the” clock to the gates are all important,in the chip design and in design with the chip. Intel. Not a FPGA but it illustrates the importance of routing.
Coming down the road (at us) One chip — microcomputer and FPGA! Altera EECS 452 – Fall 2014 Xilinx Lecture 5 – Page 8/143 Tuesday – September 16, 2014
Cyclone II EP2C70 is used on the DE2-70 Table 1–1.
Cyclone II FPGA layout From Altera.
Cyclone II logic element This is the almost in “almost unstructured”. The magic word is: configurable. From Altera.
Programmable interconnections Programmable routing is a large part of configurable. From Google Images.
Clock distribution network ▶ Modern logic design is largely based on the register transfer level (RTL) paradigm. http://en.wikipedia.org/ wiki/Register-transfer_level ▶ The state of a design is contained in registers that are all clocked at the same time. ▶ Between clock tics, combinatorial logic is used to determine the next contents of the registers.
DE2-70 RAM The EP2C70 M4K blocks contain a total of 1,152,000 bits (144,000 bytes). Can’t necessarily use as one large block . . . routing limitations. Each LE contains a D-register that can be used as a one-bit memory. The Cyclone II does not support use of a LE’s LUT as memory. Xilinx’s (but not Altera’s) LUTs support use as a 16 bit shift register. A design making heavy use of bit-serial arithmetic likely would choose a Xilinx FPGA over an Altera FPGA.
M4K RAM Table 2–7. M4K Memory Modes Memory Mode Off-fabric. 250 MHz max clock. 4608 bits (inc. parity). 4K×1 2K×2 1K×4 512×8 512×9 256×16 256×18 128×32 (not avail. true dual) 128×36 (not avail. true dual) Description Single-port memory M4K blocks support single-port mode, used when simultaneous reads and writes are not required. Single-port memory supports non-simultaneous reads and writes. Simple dual-port memory Simple dual-port memory supports a simultaneous read and write.
Multipliers signa (1) signb (1) aclr clock ena EP2C70 has 150 embedded. Off-fabric. Data A D Q ENA D Q ENA CLRN Use as: Data Out CLRN 300 9×9 150 18×18 Data B D Q ENA CLRN Input Register Output Register Embedded Multiplier Block In addition, one can implement up to 250 16 × 16 soft multipliers using M4K memory blocks. From Cyclone II documentation.
Advantages of an FPGA ▶ Low (relatively speaking) development cost of a product. ▶ Parallel processing. ▶ Field upgrade capability. ▶ Short time to market.
ASICs, FPGAs’ competition Application Specific Integrated Circuits (ASICs) implement logic directly making more efficient use of silicon. ▶ ASICs have very large non-recurring initial costs. ▶ ASICs per unit cost in volume is lower that that of FPGAs. ▶ The cross over point where FPGAs cost less than ASICS is about 100k to 200k units and is continually increasing. ▶ The time-to-market for FPGA designs is usually less than with ASICs. ▶ A FPGA can be configured in-situ in a customer’s unit.
Who makes FPGAs? ▶ Xilinx, has approximately a 47% market share. ▶ Altera, has approximately a 41% market share. ▶ Both provide free Web editions of their basic design software for use with their low end devices (where we live). ▶ Xilinx’s tool set is named ISE. ▶ Altera’s tool set is named Quartus II. ▶ Both are based on Eclipse and are very similar in use. ▶ Both support the Verilog, SystemVerilog and VHDL design languages.
The Terasic/Altera DE2-70 Ethernet 10/100M Port USB Device Port USB Blaster Port Mic in USB Host Port Line In Line Out VGA Out RS-232 Port Video In 1 Video In 2 TV Decoder (NTSC/PAL) X2 12V DC Power Supply Connector PS2 Port VGA 10-bit DAC Power ON/OFF Switch Ethernet 10/100M Controller USB Host/Slave Controller Audio CODEC 50Mhz Oscillator Altera USB Blaster Controller chipset Expansion Header 2 Altera EPCS16 Configuration Device Expansion Header 1 RUN/PROG Switch for JTAG/AS Modes SD Card S
DE2-70 features USB Blaster interface 2 Mbyte SSRAM Two 32-Mbyte SDRAM 8-Mbyte Flash memory SD Card socket SMA connector 16×2 LCD display 8 seven-segment LED digits 4 push button switches 18 toggle switches 18 red user LEDs 9 green user LEDs 50 MHz clock oscillator 28 MHz clock oscillator 24-bit audio CODEC line-in, line-out, mike-in jacks VGA DAC (10-bit high speed) 2 TV Decoders 10/100 Ethernet Contoller RJ45 Ethernet connector USB Hose/Slave USB type A and B connectors PS/2 mouse/ke
The DE2-70 power on default ▶ Used to built confidence that the board works. ▶ ▶ ▶ ▶ ▶ The default is contained in an EEPROM on the DE2-70 and is automatically loaded into the DE2-70’s FPGA on power on. Generates VGA logo display. Blinks LEDs Initializes the audio CODEC. and much more. ▶ Contained in EEPROM. Source code is available on the Terasic DE2-70 support web pages. ▶ EEPROM can be reprogrammed. ▶ Boot initializes peripherals. They might not be initialized as your application needs them.
DE2-70 reference materials The Terasic DE2-70 Resources web page http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=53&No=226&PartNo=4 contains files for: ▶ DE2-70 User Manual, ▶ DE2_70 Control Panel (for Quartus 10.0), ▶ DE2_70 Video Utility (For Quartus 10.0/10.1), ▶ DE2-70 CD-ROM (for Quartus 9.1), ▶ DE2-70 Demonstrations for QuartusII 10.0 . The two of most importance to us are the User Manual and the Demonstrations.
Definitive resources The DE2-70 schematics. Describes what actually connects to who and how. The Quartus .csv pin name list. Establishes a convention for sinal names. The pin names used on the schematics do not necessarily match those used when designing using Quartus. They, on occasion, differ between related boards such as the DE2, the DE2-70 and the DE0-nano. We make do with what we are provided. Try to avoid marching to your own drummer. Treat the DE-70 as NOT tolerant to signal levels other than 3.
Pleas Please do not solder to any of the connector pins on the DE2-70, the C5515 or the connector/adapter boards. If the jumpers that we have in lab are not adequate see Jon or me about buying or building what is needed. When doing your projects give early thought to how things will connect and order the needed parts early. It takes about a week to order and get delivery. This can be sped up by paying more for shipping, but this can get very expensive. Of course, at least one order per semester goes awry.
Hardware Description Languages ▶ Describes digital hardware, the logic elements it is made of, how they are connected and how they are clocked. ▶ Used for design,design verification and synthesis (implementation). ▶ Maps a hardware description into bit streams used to configure a FPGA. ▶ Two main HDL languages, (System)Verilog and VHDL. ▶ SystemVerilog is modeled after C. Makes assumptions, can be criticized as helping (in effect) when making mistakes. ▶ VHDL is (sort of) Ada like.
The (System)Verilog hardware description language Looks like a programming language. IT IS NOT! ▶ Does not program hardware! ▶ Describes hardware modules and how they are interconnected. ▶ The syntax is very closely modeled on that of C. It is a hardware description language.
Brief history of the Verilog HDL ▶ Seeds planted about 1985. Originally intended as a simulation language. ▶ Sold to Cadence in 1990. Capability for synthesis was gradually added. ▶ Verilog-1995 standard. ▶ Verilog-2002 standard ▶ Verilog IEEE standard 1364-2005 issued. ▶ Initial SystemVerilog standard, 1800-2005. ▶ SystemVerilog Standard merged with Verilog Standard, 1800-2009. ▶ Current IEEE SystemVerilog standard version, 1800-2012.
Learning SystemVerilog Common quotes: ▶ You learn by doing. ▶ You learn from your mistakes. ▶ Start simple, slowly add complexity. My background is VHDL (an alternative HDL). I’ve done a moderately small amount design using SystemVerilog. For both languages I’ve done a lot of learning. One thing that I’ve learned is that when something goes wrong it is important understand what and why. Otherwise nothing has been learned.
Some Verilog and SystemVerilog references http://en.wikipedia.org/wiki/Verilog http://en.wikipedia.org/wiki/SystemVerilog http://www.asic-world.com/systemverilog/tutorial.html Digital System Design with SystemVerilog, Mark Zwolinski, Prentice Hall, 2010. Download the SystemVerilog standard . . . it’s free! http://standards.ieee.org/events/edasymposium/stds.html Complements of Accellera.
Comments on (System) Verilog references ▶ I’ve seen the claim (on the web) that the SystemVerilog standard makes a good tutorial. With a bit of caution, I have found the standard to be very useful. Having a previous bit of Verilog background helps deciding what to pay attention to and what to skip over. ▶ There don’t seem to be many texts focused on design and synthesis using SystemVerilog. There are several that focus on the use of SystemVerilog for design verification and benchmarking.
Comments about standards ▶ If you are earning your living doing programming and or hardware design, you should have a copy of the associated standards. Typically we depend upon secondary sources such as textbooks and web articles. Where did they get their information? ▶ It is often useful to read the standards. ▶ Standards are notoriously hard to read. I strongly feel that it’s worth the effort to at least look at them. The Verilog and SystemVerilog standards are readily available on the web.
Verilog DIY learning links http://www.asic-world.com, in particular: http://www.asic-world.com/verilog/verilog_one_day.html Altera’s HDL design examples: http://www.altera.com/support/examples/exm-index.html How does SystemVerilog extend Verilog? http://en.wikipedia.org/wiki/SystemVerilog There are also two EECS 270 tutorials linked to on the lab exercise 3 write-up. Consider using SystemVerilog.
Altera’s Quartus II design software ▶ An Eclipse GUI based development system. ▶ Supports the development flow from design entry to loading the design bit file into a FPGA and/or loader EPROM. ▶ EECS 452 uses CAEN’s subscription edition on Windows 7. ▶ A free web edition is available for Windows and Linux. ▶ I’m running version 13.0 SP1 on Windows, Ubuntu and Debian. http://dl.altera.com/13.
Some Quartus II resources An introduction to Quartus II. http://www.altera.com/literature/manual/quartus2_ introduction.pdf Quartus II Handbook v14.0a10 (Complete Three-Volume Set) (23 MB). http://www.altera.com/literature/lit-qts.jsp A bit overwhelming in size. Take a peek to see what’s there. Using the Quartus II Software: An Introduction (ODSW1100) 72 minutes Online Course . Free, registration required. http://www.altera.
Processing a design A Verilog design description describes the ▶ The registers making up a device. ▶ The interconnections between registers. ▶ The timing of changes in the register states. A series of Quartus programs ▶ synthesizes the design to the basic logic element level. ▶ fits the result into the FPGA and routes signals. ▶ generates a .sof file to be used to configure the logic elements and establish routing segments and .pof file for possible use in programming the boot EPROM.
Quartus II file extensions Quartus II uses and/or generates file using a various file extensions. The extensions most important to us are: .v Verilog text file. .sv SystemVerilog text file. .qpf Project description file. .csv Comma separated values. Normally used to generate the working pin name description file. .qsv Pin description list. Often there is a default version that can be used to generate the working version. .sdc clock definitions. .sof Bit output file used to program the FPGA. .
.qsf file comments ▶ This file has the name of the top file and the extenstion .qsf. ▶ It is used to map signal/wire names to pins on the FPGA and to specifify other information associated with that pin such as logic time, pull-up or pull-down resistor. ▶ I downloaded my starting .qsf versions (which I keep in a separate directory from the Altera web site. These are specific to the chip being used. ▶ Use assignments — Import Assignments to load the master list into a project specific .qsf file.
DE2-70 .
DE0-Nano .qsf file snippet #============================================================ # Accelerometer and EEPROM #============================================================ set_location_assignment PIN_F2 -to I2C_SCLK set_location_assignment PIN_F1 -to I2C_SDAT set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK set_instance_assignment -name IO_STANDARD "3.
Selecting the I/O standard ▶ The Altera FPGA IO blocks support use of a number of logic drive/receiver standards. ▶ These are generally selected per IO block. All pins in a given block must use the same standard. ▶ The standards supported will vary between logic families. ▶ For the DE2-70 the default (which is?) has proven adequate for most cases. ▶ If changes are needed to a .qsf file, make a copy of the supplied file, rename it to the current project and make the desired changes.
.sdc file comments ▶ Not strictly needed, but . . . . ▶ Used to describes the clocks used by a design. Typically our designs will primarily use a 50 MHz clock. But not necessarily exclusively. ▶ Timing information is used when routing and optimizing a a design. ▶ Information along with chip information to calculate expected set up and hold times and the maximum allowable clock frequency. Most small, lab exercises just work.
From my .sdc file This is a mixture of what I originally entered and wizard generated text. I copy and rename the file from another project. Give it the name of the top file with the .sdc extension. This seems to be read and overwritten automatically. I had to split the CLOCK_25 line into two lines to make it fit here. Make it back into one line if you use it. # Clock constraints create_clock -name "CLOCK_50" -period 20.
Dealing with a pin conflict In the lab exercise you were asked to add a line to your .qsf file to avoid a pin assignment problem. The following is an alternate way to accomplish the same task. Pin AD25 of the DE2-70’s FPGA has two uses. One is as a JTAG pin and the second as an input/output pin. The DE2-70 connects this pin to slide switch iSW[7]. When a design uses iSW[7] this will lead to a fatal error.
Creating a project EECS 452 – Fall 2014 Lecture 5 – Page 45/143 Tuesday – September 16, 2014
Specifying the FPGA (DE2-70) EECS 452 – Fall 2014 Lecture 5 – Page 46/143 Tuesday – September 16, 2014
Almost ready to go EECS 452 – Fall 2014 Lecture 5 – Page 47/143 Tuesday – September 16, 2014
It remains to . . . ▶ Import a .qsf file. This maps pins on the FPGA to name space. These can vary depending on the board and where you got the file from. ▶ Remove a pin conflict between a pin that is connected to a slide switch and Quartus defaults as a programming pin. This likely is already done in the .qsf file used in the lab. ▶ Probably should supply an .sdc file to define the clocking. This enables the timing analyzer to check for proper set-up and hold times.
Quartus II screen shot EECS 452 – Fall 2014 Lecture 5 – Page 49/143 Tuesday – September 16, 2014
The warning windows The warning and the critical warning windows are your friends. If the SV/V compiler encounters a inconsistency (e.g., declared array size does not match the size used in an expression) rather than throw an error it will make a decision about how to resolve it and continue on. When writing code it is a good philosophy to say what you mean and mean what you say. (I.e., don’t get clever!) Usually the warnings alert you to when the compiler has had to make a decision.
Structure of a (Verilog/SystemVerilog design Off-FPGA Hardware pins/pads FGPA Fabric top module module a module a EECS 452 – Fall 2014 module b module etc.
Comments on module structure ▶ (System)Verilog is very C like. ▶ Multiple modules can be present in a source file. ▶ Consider naming the top module with the project name followed by _top. For example my VGA_nano project top file is named VGA_nano_top.sv. ▶ The top level module port signal names need to match the names in the assigned .qsf file. The .qsf file assigns signal names to actual pins on the FPGA. ▶ Occasionally one wants to combine two existing projects each having its own top file.
Module port declaration and using it Definition: module module_name ( direction name1, direction name2, input clk, // typically 50 MHz input reset_n ); Directions are typically input, output and inout. Instantiation: module_name instance_name ( .name2(parameter2), .name1(parameter1), .reset_n(reset_n), .
An Altera example EECS 452 – Fall 2014 Lecture 5 – Page 54/143 Tuesday – September 16, 2014
Altera’s addsub.v example module addsub ( input [7:0] dataa, input [7:0] datab, input add_sub, // if this is 1, add; else subtract input clk, output reg [8:0] result ); always @ (posedge clk) begin if (add_sub) result <= dataa + datab; else result <= dataa - datab; end endmodule This is a behavioral description of what is to be accomplished. Note the automatic promotion of the number of bits.
Structural and Behavioral descriptions Structural — Pretty much working at the gate level. Organizing various types of basic logic elements and describing how they are connected. If you want to add two twelve bit signals you have to design and build the adder. Behavioral — Pretty much saying what you want. Not so much concerned with how it is accomplished. For example specifying that two twelve bit signal values be added together without specifying how this is to be physically accomplished.
Verilog’s numbers Size (decimal number, always), followed by the base, followed by the value, in that base.
Verilog’s base logic elements and nand nor or xor xnor These six logic gates can have only one output and multiple inputs. The output is specified first in the instantiation. Example and gate declaration: and a1 (out, in1, in2, in3); buf not These can have multiple outputs but only one input.
Full Adder outputs inputs cn sn bn an cn−1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 EECS 452 – Fall 2014 Åçìí Å~êêó Åáå ~ Ä Lecture 5 – Page 59/143 ë ëìã Tuesday – September 16, 2014
Full Adder — Structural module full_adder(a,b,cin,sum,cout); input a,b,cin; output sum, cout; xor (sum,a,b,cin); and (a0,a,b),(a2,a,cin),(a3,b,cin); or (cout,a0,a1,a2); endmodule This is somewhat on the “obsessed with detail” side of life. We rarely, if ever, want to work at this low of level of abstraction. At least it is a level of abstraction above specifying how to arrange individual transistors.
Verilog’s operators The point of the next three slides is to make you aware of the operators available in Verilog. These generally cause the required logic to be synthesized. For example, if we have two 16-bit reg items we can add them together and place the result in a third (which might be one of the two original) by writing: a <= b+c; Verilog takes on the responsibility of supplying the needed adder logic. Each time we write an expression like this we create another adder.
Verilog’s operators part 1 Table 11-1—Operators and data types Operator token Name = += binary assignment operator -= /= *= %= &= |= ^= Operand data types any binary arithmetic assignment operators integral, real, shortreal binary arithmetic modulus assignment operator integral binary bit-wise assignment operators integral >>= <<= binary logical shift assignment operators integral >>>= <<<= binary arithmetic shift assignment operators integral ?: conditional operator any + - ! ~ &
Verilog’s operators part 2 % & | ^ ^~ ~^ binary arithmetic operators integral, binary arithmetic modulus operator integral , binary bit-wise operators integral binary logical shift operators integral >>> <<< binary arithmetic shift operators integral && || -> <-> binary logical operators integral, real, shortreal binary relational operators integral, real, shortreal binary case equality operators any except real and shortreal >> << < <= === == >= != ==? ++ > !== !=? -- binar
Verilog’s operator precedences Table 11-2—Operator precedence and associativity Operator () + [] :: .
SystemVerilog’s data types In Verilog there are two primary data types, wires (wire) and registers(reg). Wires represent connections. Registers correspond to variables to hold values. The default data type is a one bit wide wire. Note: registers are not necessarily actual registers. SystemVerilog introduced logic type to replace the use of wire and reg. SystemVerilog is a weakly typed language.
Full adder — Behavioral module FullAdder(input a, b, cin, output sum, cout); assign sum = a^b^cin; assign cout = (a&b)|(a&cin)|(b&cin); endmodule ^ exclusive-or | inclusive-or & and I parenthesized the and operations even though I didn’t have to. It is generally better to use parentheses than not. For this type of application, one likely would work at this level of abstraction.
Full adder — Behavioral, again module FullAdder(input a, b, cin, output reg sum, cout); always @(*) {cout,sum} = a+b+cin; endmodule An even more abstract view. Note the automatic extension of one-bit bit operations to two bits caused by the concatenation on the result side of the = assignment. At least this is what I think has happened. This example is based on one found at http://www.asic-world.com/verilog/syntax2.html.
Full adder test Each full adder implementation should give the same result. module FullAdder_top ( output [17:0] oLEDR, input [17:0] iSW ); FullAdder_S fa0 (iSW[1], iSW[2], iSW[0], oLEDR[0], oLEDR[1] ); Testing using switches: FullAdder_B0 fa1 (iSW[1], iSW[2], iSW[0], oLEDR[4], oLEDR[5] ); ▶ iSW[0] carry in ▶ iSW[1] a value ▶ iSW[2] b value Displaying using red leds: ▶ 0,4,8 the sum out ▶ 1,5,9 the carry out This was a good learning exercise. EECS 452 – Fall 2014 FullAdder_B1 (.cout(oLEDR[9]), .
Unrestricting the signal order The order of the signals in the instantiation of a module normally MUST match the order in the associated module definition. For modules having a large of number of signals to connect this can be a recipe for disaster. Today’s common wisdom is that having to match order is not a good thing. That is, one should not require it. Using the construct shown in the FullAdder_B1 instantiation removes the matching order requirement.
Blocking versus non-blocking assignments How does c = a; d = c; differ from c <= a; d <= c; ? In an FPGA everything CAN happen all at once.
SystemVerilog procedural statements Selection statements — if–else, case, casez, casex, unique, unique0, priority Loop statements — for, repeat, foreach, while, do...while, forever Jump statements — break, continue, return From IEEE Standard 1800-2009. I’m mixing my standards between this slide and the next, sorry.
Syntax for looping statements Expanding on the looping statements: function_loop_statement ::= (From Annex A - A.6.
For loop example always_comb // always @(word) begin is_odd = 0; for (i=0; i<=7; i=i+1) begin is_odd = is_odd xor word[i]; end end assign parity = is_odd; Whoa! This is combinatorial logic. It sure looks sequential. What does the resulting logic look like? From Y.T.Chang 2001 CIC/Xilinx slide.
For loop example result word[7] parity word[6] word[5] word[4] word[3] word[2] word[1] word[0] 0 EECS 452 – Fall 2014 Lecture 5 – Page 74/143 Tuesday – September 16, 2014
Lab exercise 3 Exercise serves as an introduction to the DE2-70, Verilog and Quartus II. On the hardware side you will working with the ▶ slide switches, ▶ push button switches, ▶ LEDs, ▶ seven-segment digits, ▶ CODEC (A/D and D/A converters for audio), ▶ direct digital synthesis of a sine wave. In today’s lecture we touch on only a few aspects of the exercise.
Comments on the DE2-70 CODEC support ▶ Same CODEC part is used on the DE2-70 as on the DE2. ▶ Large chunks of CODEC support code from http://courses.cit.cornell.edu/ece576/DE2/NoiseCancel/AUDIO_DAC_ADC.v and Altera. Module from EECS 270. ▶ I believe that operation depends upon the CODEC to being previously initialized. This generally happens when the default configuration file is loaded into the FPGA when the power is applied.
CODEC device used on DE2-70 The CODEC is a Wolfson WM8731 audio CODEC. http://www.wolfsonmicro.com/products/codecs/WM8731/ From the Wolfson web site.
The WM8731, what and how “Stereo 24-bit multi-bit sigma delta ADCs and DACs are used with oversampling digital interpolation and decimation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported.” (From the WM8731 web site.) The lab exercise using the WM8731 is reasonably self-contained. However, if you need more information (perhaps for use in a project): ▶ Read the data sheet. (Also present on the DE2-70 System CD-ROM.) ▶ Read section 6.
DE2-70 schematic, CODEC C39 VCC33 1u R99 4.7K R100 4.7K LINE IN 5 2 4 1 3 1u NCL R NCR L GND J11 C38 PHONE JACK B VCC33 R108 R109 2K 2K R101 R102 4.7K 4.
DE2-70 CODEC pin assignments Signal Name FPGA Pin No. Description AUD_ADCLRCK PIN_F19 Audio CODEC ADC LR Clock AUD_ADCDAT PIN_E19 Audio CODEC ADC Data AUD_DACLRCK PIN_G18 Audio CODEC DAC LR Clock AUD_DACDAT PIN_F18 Audio CODEC DAC Data AUD_XCK PIN_D17 Audio CODEC Chip Clock AUD_BCLK PIN_E17 Audio CODEC Bit-Stream Clock I2C_SCLK PIN_J18 I2C Data PIN_H18 I2C Clock I2C_SDAT Table 5.12. Audio CODEC pin assignments. From DE2-70 User manual.
Need a fast D/A? Assuming that the VGA DAC is not being used to generate a VGA display it can be used as up to a three channel DAC. A standard 640 × 480 display pixel clock rate is 25 MHz. DAC clock rates of up to around 75 MHz likely are possible. Consult the data sheet.
A digression, the PS2 connector This is not used in any of the lab exercises but is a resource that might be useful (and has) at project time. 5 4 3 RXD R44 330 R45 330 2 1 LEDR UART_RXD J2 VCC33 D ▶ TXD LEDG UART_TXD 5 9 4 8 3 7 2 6 1 D Can be used other than to connect to a PS2 device.
Implementing a DDS sine table ▶ Use a case statement with assignments. Simple and easy. This is one of ways described in the lab exercise. A large table requires use of a lot of logic elements. A 256 × 16 table uses 4096 LE D-registers. ▶ Indexed arrays are supported by Verilog 2001. These can be initialized by reading an external initialization file (constructs exist to do this) or by using an initial block.
Sine generation using a case statement always@(negedge clock) counter <= counter + FTV; always@* begin case(counter[9:6]) 0 : dataOut 1 : dataOut 2 : dataOut 3 : dataOut 4 : dataOut 5 : dataOut 6 : dataOut 7 : dataOut 8 : dataOut 9 : dataOut 10 : dataOut 11 : dataOut 12 : dataOut 13 : dataOut 14 : dataOut 15 : dataOut default : dataOut <= endcase end EECS 452 – Fall 2014 <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= 0; 12539; 23170; 30273; 32767; 30273; 23170; 12539; 0; -12539; -23170; -30273; -32767; -
Sine generation using an array reg [15:0] sine_table [15:0]; initial begin sine_table[0] = 0; sine_table[1] = 12539; sine_table[2] = 23170; sine_table[3] = 30273; sine_table[4] = 32767; sine_table[5] = 30273; sine_table[6] = 23170; sine_table[7] = 12539; sine_table[8] = 0; sine_table[9] = -12539; sine_table[10] = -23170; sine_table[11] = -30273; sine_table[12] = -32767; sine_table[13] = -30273; sine_table[14] = -23170; sine_table[15] = -12539; end always@(negedge clock) counter <= counter + FTV; always @(*)
Sine generation using SystemVerilog reg [15:0] sine_table[0:15] = ’{0, 12539, 23170, 30273, 32767, 30273, 23170, 12539, 0, -12539, -23170, -30273, -32767, -30273, -23170, -12539}; always@(negedge clock) counter <= counter + FTV; always @(*) dataOut = sine_table[counter[9:6]]; ▶ Made the needed changes to my previous .v file. ▶ Note the use of ’{ as the opening brace. ▶ Note the top line sine_table index order. ▶ Changed the file extension to .sv. ▶ Recompiled and ran.
Using QuartusII Megafunctions In Quartus, Tools — MegaWizard Plug-In Manager Usually will create a new one. Though editing an existing one is something that I’ve frequently done.
Megafunctions continued Some are free, some are not. I think that the non-free ones are in the MegaStore. Non-free can usually be used tethered and are likely time-duration limited. My most common use has been RAM, ROM and FIFO. There is documentation. You have to hunt it up.
Specifying a ROM EECS 452 – Fall 2014 Lecture 5 – Page 89/143 Tuesday – September 16, 2014
Memory Initialization File .
More .mif information .mif files are not part of the Verilog standards. ▶ Binary radix is BIN. ▶ Octal radix is OCT. ▶ Hexadecimal radix is HEX. ▶ Unsigned decimal is UNS. ▶ Signed decimal is DEC. There are also some address/value pair syntax rules. It is usually relatively easy to write a C program or MATLAB script to automatically generate a .mif file. Or, at least, its contents for copy and paste.
Example .mif sine table generator /* * main.c * * slapdash quick and dirty sine table .. not * checked for symmetry, etc. * * initial version .. 02 Oct 2011 .. K.Metzger * */ #include #include #include #define N 256 #define pi 3.14159265 void main(void) { unsigned ctr; int v; FILE *out; out = fopen("sine_rom.
Comments ▶ My normal convention to place the file name on the first line. ▶ Did not pay attention to how values are rounder/truncated. There are applications where getting the table right is very important. Ours is not one of them, but you should be aware that the code is a bit dirty. ▶ Only prints out the table entries. Have to hand add the descriptor information. ▶ I did pay attention to the return when opening the output file. ▶ I did close the output file before terminating.
Verilog multiplication and Cyclone II In Exercise 3 a multiplication is involved in computing FTVs. At the Verilog level one can write assign out = a*b. What’s behind the implementation? Using Google the following two documents were found: ▶ Recommended HDL Coding Styles. ▶ Embedded Multipliers in Cyclone II Devices. Figure 12–2. Multiplier Block Architecture signa (1) signb (1) aclr clock ena Data A D Example 11–1.
Overflow lecture material Variations on Blinky for the DE2-70. Crossing time boundaries Bit serial interfacing. PMod D/A and A/D. DE0-Nano. Some comments. Last one out should close the lab door!!!! Please keep the lab clean and organized. Always code as if the guy who ends up maintaining your code will be a violent psychopath who knows where you live.
The FPGA Blinky variations ▶ The first variation is a “just do it” LED blinker. Synthesizes using a “dreaded” latch. ▶ The second variation replaces the latch of the first variation using a register. ▶ The third variation is slightly more complicated blinking two LEDs in a simple pattern. This is meant to illustrate how one might code a two process state machine.
Blinking an LED // File name: Blinky.sv // // 10Sep2013 .. initial version .. K.Metzger // module Blinky ( output LEDR[0], input CLOCK_50 ); logic led_bit, clk; logic [24:0] counter; // top level module for this example // signal names must match those in .qsf file // sized to generate 0.
Blinky comments ▶ A common problem is mismatching the top level signal names with the ones used in the .qsf file. This is NOT flagged as an error! ▶ What happens to led_bit when counter is not 0? A latch is synthesized. ▶ The values of led_bit and counter change only on the positive edge transition of clk. ▶ 25 bits allows counts of up to 33,554,432. ▶ One of my SystemVerilog fantasies is that counting down to 0 simplifies the end test logic. ▶ SystemVerilog is a weakly typed language.
Blinky using registers // File name: Blinky_D.sv // // 10Sep2013 .. initial version .. K.
Blinky_D comments ▶ I got sort of canonical. The counter was already a register because of the way it was being used. At least I think it was. ▶ The led_bit is aways updated in the always_ff block. The next_led_bit = led_bit determines what the updated value is if there isn’t a change to be made.
Blinky_state part 1 // File name: Blinky_state.sv // // 10Sep2013 .. initial version .. K.Metzger // 17Sep2013 .. made Blinky more complicated and added states ..
Blinky_state part 2 always_comb begin next_counter = counter-1; next_time_counter = time_counter; next_red_led_bit = red_led_bit; next_green_led_bit = green_led_bit; next_state = state; if (counter == 0) begin next_counter <= 25000000-1; next_time_counter <= time_counter + 1; end case (state) starting: begin if (time_counter == 2) begin next_time_counter <= 0; next_red_led_bit <= 1; next_state <= turn_on_red; end end turn_on_red: begin if (time_counter == 4) begin next_time_counter <= 0; next_green_led_bit
Blinky_state comments ▶ Idles for one second with both LEDs off. Turns the red LED on. After two seconds turns on the green LED. After 3 more seconds turns both off. Repeats. ▶ Uses an enum statement to define the states and a case statement to select between states. ▶ The “present” and “next” paradigm is reasonably common. At least one FPGA test uses “present” as a prefix as is done with “next”. ▶ The always_ff always loads the next value into the current.
Loading Blinky into the FPGA ▶ There are two ways to get access to the USB Blaster programmer. 1. On the tool bar at the top of the Quartus II window go to Tools---Programmer. 2. In the Task window where you clicked Compile Design double click Program Device (Open Programmer). ▶ Make sure that the DE2-70 RUN/PROG switch (left middle side) is in the RUN position. ▶ The programmer support is normally configured properly and all one needs is to click the Start button.
Making Blinky the default ▶ Quartus generates two output files. One has a .sof extension and is for loading directly into the FPGA. The other has a .pof extension and is for loading into the power-on boot EEPROM. ▶ To program the EEPROM the DE2-70 RUN/PROG switch needs to be in the PROG position. ▶ In the programmer window: ▶ ▶ ▶ ▶ ▶ Change the Mode to Active Serial Programming. Add File, select output_files. You should see your .pof file listed. Click on it then on open.
Restoring the default default ▶ The Terasic supplied default start-up code can be found in the DE2-70_v.1.4.0_CDROM file. ▶ Mouse down through DE2_70_demonstrations, DE2_70_Default to find the DE2_70_Default.qpf file. ▶ The included .sof and .pof were generated using a earlier version of Quartus and might not be programmable using the current version’s USB Blaster. I generally recompile. ▶ Program the EEPROM using the newly generated .pof as described in the preceding slide.
The FPGA breakout board ▶ Connects 40-pin IO port to 8 6-pin connectors. ▶ 6-pin connectors compatible with Digilent PMod boards. http://www.digilentinc.com/ Products/Catalog.cfm? NavPath=2,401&Cat=9. ▶ Supply voltage jumper selectable, +3.3V and +5.0V. Remove jumpers when power not needed! ▶ Pin 1 light colored. ▶ Also useful as test points.
DE2-70 FPGA breakout board connections 08/05/12 7:08:14 PM f=1.50 C:\Users\Kurt\Documents\eagle\Fall_2011_DE2-70_breakout\DE270Break.
DE2/DE2-70/DE0-Nano GPIO names pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DE2 GPIO_x[0] GPIO_x[1] GPIO_x[2] GPIO_x[3] GPIO_x[4] GPIO_x[5] GPIO_x[6] GPIO_x[7] GPIO_x[8] GPIO_x[9] VCC5 GND GPIO_x[10] GPIO_x[11] GPIO_x[12] GPIO_x[13] GPIO_x[14] GPIO_x[15] GPIO_x[16] GPIO_x[17] GPIO_x[18] GPIO_x[19] GPIO_x[20] GPIO_x[21] GPIO_x[22] GPIO_x[23] GPIO_x[24] GPIO_x[25] VCC33 GND GPIO_x[26] GPIO_x[27] GPIO_x[28] GPIO_x[29] GPIO_x[30] GPIO_x[31]
Bit-serial data transfers ▶ Moore’s law has been running for some time now. Space on a chip become very inexpensive, pins and interconnections have not. ▶ Many devices have relatively low data rates. Maybe 1M 8 or 16-bit words per second. ▶ Modern run-of-the-mill digital drivers often can drive PCB-traces and actual wires at rates of 50 Mbs and often higher. ▶ For many of the synchronous bit-serial protocols everything is edge driven.
Clock domain crossings “A clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock.
CDC references ▶ Understanding clock domain crossing issues, Saurabh Verna, EE Times–India, December 2007. ▶ Clock Domain Crossing (CDC) Design & Verification Techniques Using System Verilog, Clifford E. Cummings. ▶ http://www.fpga4fun.com/CrossClockDomain.html.
g clock domain and mitigation Metastability s names shown ectly used. For C2 imply the tion clocks rey A and B are nd destination ectively. Also, stination flops positive edge 1. 2. In theory, a flip-flop can take a very long time to decide. ▶ It is not possible to guarantee that a metastable state will not occur. ▶ Fast logic and slow clock rates help, but . . . . ▶ It is possible to reduce the probability of a metastable state to a very small number.
Metastability cause ts Q X Q th setup time clock b hold time X clock a clock b ▶ It takes time for things to get ready to happen and then to happen. ▶ If there isn’t adequate time, things go wrong. ▶ In theory, it can take a very long time to settle down. ▶ Metastability can be a problem in a FPGA’s clock distribution network even in a single clock domain. ▶ Quartus II’s timing analyzer checks to whether or not the required setup and hold times are met.
Generic synchronous bit-serial send/receive transmitter connection receiver received_flag frame_sync clock_a control logic shift register shift_clock bit_serial_data control logic ? clock_b shift register register parallel_data ▶ The transmitter is in charge and relatively easy to design. ▶ The design of the receiver is the challenge.
An answer is ? ▶ As late as possible. ▶ When using a well designed protocol, it should be possible to clock the receiver and generate the received_flag using the supplied clock and frame synchronization signals. ▶ The only signal that needs metastabilty protection should be the received_flag. ▶ If this is not the case, the protocol is not properly designed or the receiver designer needs to think more.
Commonly encountered protocols ▶ SPI (serial peripheral interface) ▶ ▶ ▶ I2S (Inter-IC, Integrated Interchip Sound) ▶ ▶ Used to interconnect audio devices together. I2C (Inter-Integrated Circuit) ▶ ▶ Not standardized. Supported by many devices such as A/D and D/A chips. Multi-master, low speed with addressability. UART (Univeral asynchronous receive/transmit) ▶ ▶ Dates from the 1920s. Has been somewhat updated. Uses pre-agreed upon clock rate. There are many, many more.
The SPI protocol ▶ A synchronous bit-serial protocol. ▶ Originated by Motorola but not standardized. ▶ Many devices use a SPI-like protocol. For example, the PMod A/D and D/A converter modules. ▶ The Wikipedia has a nice discussion: http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus ▶ Meant to be easy to implement and work with. ▶ Typical transfer size are 8 and 16 bits. ▶ Bi-directional. Send a word, receive a word, with latency.
SPICCR SPIDCR1 SPICDR SPIDCR2 SPI_RX/MISO B6 B7 B5 B4 B3 B2 B1 B0 SPI timing example SPICMD1 Clock Generator SPICMD2 SPI_CSn/SS SPISTAT1 SPISTAT2 SPI_CLK Sequencer SPI Interrupt to CPU SPI_CS Figure 6. SPI Mode 2 Transfer (CKPn = 1, CKPHn = 0) SPIDAT2 SPI_RX SPIDAT1 SPI_CLK/SCK SPI_TX SPI_TX/MOSI B6 B7 Use Case Statement B5 ntended for communication between the DSP and up to four SPI-complaint slave devices.
My DIY SPI timing example FPGA changes output on rising edges FPGA samples on falling edges TI RX TI DX Start of transfer Transmitter shift register loaded Transmit register empty flag set EECS 452 – Fall 2014 Lecture 5 – Page 120/143 End of Receive transfer flag set Receive register loaded Tuesday – September 16, 2014
The I2S protocol ▶ Used by CODEC chips in the C5515 and the DE2-70 for data transfer. ▶ Several modes of operation, stereo, mono, etc. ▶ When C5515 is a master the word rate is fixed and constant. When C5515 is slave the edge timings from the FPGA rule! ▶ A reasonable use is an reverse channel from FPGA to C5515. ▶ A useful reference is the C5515 I2S User’s guide, SPRUFX4.
N N N - - 1 2 3 DATA 3 2 1 N N N - - 1 2 3 0 I2S timing example LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data LD(n+1) RD(n) = n'th sample of right channel data Figure 1-8. Timing Diagram for I2S Mode I2S FS LEFT CHANNEL RIGHT CHANNEL I2S_CLK ti.com Architecture Table 1-1.
The I2C protocol ▶ Eight data bits and eight bits address plus two handshake bits. ▶ Ack bit is driven by addressed device, if present and ready. ▶ Used by the CODEC in the DE2-70 for configuration. ▶ The FPGA CODEC and NTSC video decoder devices are configured using I2C. ▶ We have a couple of CMOS digital cameras that are I2C configured.
clock signals to permit that transfer. Any device that is addressed by this master is considered a slave during this transfer. The I2C connection and timing An example of multiple I2C modules that are connected for a two-way transfer from one device to other devices is shown in Figure 2. www.ti.com Figure 2. Multiple I2C Modules Connected 2.6 VDD Serial Data Formats Peripheral Architecture Figure 7 shows an example of a data transfer on the I2C-bus.
The UART protocol ▶ Universal asynchronous receiver/transmitter (UART). ▶ The UART has been around for a long time. ▶ Asynchronous, clock is assumed. No clock domain boundary to cross! ▶ Usually eight data bits plus optional parity. Two or three support bits. ▶ There exist “standard” baud (bits/second) rates. ▶ Designed to be robust to clock offset/drift. ▶ http://en.wikipedia.org/wiki/Universal_asynchronous_ receiver/transmitter.
The UART frame mark space start bit b0 b1 b2 b3 b4 b5 b6 b7 time stop bit ▶ Frame start is detected by a mark to space transition. (Assuming the system is idling in mark.) ▶ A one bit time offset is used to sample and verify that a space bit is present. ▶ The next 8 bits are sampled using a time step of one bit time. ▶ The last bit is a mark and is called a stop bit. Multiple stop bits might be present. ▶ The clocks between transmitter and receiver can be off frequency by as much as about 5%.
The FT232R UART/USB breakout ▶ Used to communicate UART data (8-bit) over USB. ▶ Powered by the USB connector’s 5 Volts. Regulates this down to 3.3 Volts. ▶ Supports RTS/CTS handshake. ▶ Max baud clock is counted down from 3 Mbs. Integer divide factor. ▶ I’ve successfully used these at 1.5 Mbs and 3.0 Mbs. ▶ I’m using FTDI’s D2XX direct drivers on the RPi (the USB end). I located a special build for RPi’s hard float. FTDI’s V1.1.12 only supports soft float.
Bit-serial comments ▶ The PMod boards are pretty much intended for use on FPGA boards made by Digilent. The DE2-70/DE0-Nano breakout board allows their use on these Terasic boards as well. ▶ Using an adapter card or cable one can plug a PMod A/D and/or PMod D/A directly to a C5515 breakout board 6-pin connector. I’ve tested using SPI and I2S. ▶ Once can implement your own serial protocol. A few semesters a project (Seymour) bit-banged a four bit protocol between an FPGA and the Raspberry Pi.
Synchronizer module // File name: synchronizer.sv // // 09Aug2012 .. version started .. K.
The Digilent PMod-DA2 module Analog Outputs 2 DAC121S101 D/A Converter Sync, Clock D2 DAC121S101 D/A Converter J2 Connector J1 Connector D1 GND VCC The PMod-DA2 uses two National Semiconductor DAC121S101 12-bit digital-to-analog converters with rail-to-rail output. Uses a bit-serial interface. Maximum serial clock rate is 30 MHz. Operates using supply voltages in the range 2.7V to 5.5V. Figure from the PMod Digilent data sheet.
The DAC121S101 D/A Max serial clock : 30 MHz Data uses offset binary. Analog output updates on 16th shift clock falling edge. From the National Semiconductor data sheet.
How to make the D/A work Here are some observations/guesses about control of the D/A. These are based on the timing timing diagram and written signal descriptions contained in the data sheet. Use of a state machine in the D/A control logic is assumed. ▶ sync_n can remain high between updates going low when a serial transfer is to start. ▶ The start of a serial transfer is detected by sampling sync_n using the rising edges of sclk. ▶ Data bits are sampled on the falling edges of sclk.
Starting simple with the D/A A simple test is to run a counter and send the count values to the D/A and observe the waveform. About as basic test you can do. Check the schematic and data sheet to ▶ determine the part number. ▶ see how the part is designed into the board. ▶ find the PMod pin signal assignments. Check the D/A data manual to determine ▶ how it works. Actually, to learn how to make it work. ▶ the signal timings. ▶ the mapping from digital input values to output voltages.
The Digilent PMod-AD1 module P1: CS ADC 1 Filter P1 P2 P3: Data 2 ADC 2 Filter P4: Clk P3 P4 P5: GND P5 P6: Vcc P6 J2 Connector J1 Connector P2: Data1 AD1 Circuit Diagram The PMod-AD1 uses two National Semiconductor ADCS7476 12-bit analog-to-digital converters supporting rail-to-rail input. Uses a bit-serial interface. Maximum serial clock rate is 20 MHz. Operates using supply voltages in the range 2.7V to 5.25V. Figure from the PMod Digilent data sheet.
The ADCS7476 A/D Max serial clock : 20 MHz Max sample rate: 1 MHz Data uses offset binary. Input switches from track to hold on falling edge of the sync signal. From the National Semiconductor data sheet.
Comments ▶ Timing diagrams typically show what one can get away with not necessarily best practice. ▶ Notice the runt SDATA digit. This is what can get away with. I really wouldn’t design to cause this. ▶ Relative to the clock shown I started CSbar half a clock earlier. This gives a more full data bit. ▶ The SDATA bits are sampled at the instant at which the sclk falling edges are started. ▶ I can do this because I sample the bit at the same time as I start the edge to fall.
DIY directed study DSP with FPGAs ▶ On Amazon, about $122. ▶ Uses Verilog, now includes some VHDL. ▶ 930 pages. ▶ Published May 2014. ▶ Uses Quartus II web edition. ▶ Includes source code in appendices. ▶ Focuses on communications applications. ▶ Signed fixed point and floating point IEEE library examples. ▶ Overview on parallel all-pass IIR filter design. From the Amazon web site.
FYI: Terasic DE0-Nano http://www.terasic.com. tw/cgi-bin/page/archive. pl?Language=English& CategoryNo=139&No=593 ▶ 22,230 LEs, 32 MB SDRAM (mounted on back side), $79. ▶ 40-pin headers can match those on DE2-70. ▶ Has been used in past EECS 452 projects. ▶ Have a couple of units on-hand. ▶ Built in USB-blaster.
DE0–Nano features ▶ Cyclone IV FPGA, 22,320 logic elements, 594 Kbits M4K memory, 66 embedded 18 × 18 multipliers, 4 PLLs and 152 FPGA I/O pins. ▶ USB powered. ▶ Two 40-pin expansion headers. ▶ One 26-pin header provides 16 GPIO pins and analog input pins. ▶ 32 MB SDRAM, 2Kb I2C EEPROM. ▶ 8 green LEDs, 2 debounced push buttons and 4 DIP switches. ▶ 3 axis accelerometer. ▶ 8-channel, 12-bit A/D converter, 50 ksps to 200 ksps. ▶ 50 MHz oscillator. ▶ Nominal cost: $79, academic: $59.
DE2/DE2-70/DE0-nano support materials Terasic makes available the schematics, user’s manual, demo source code and other materials for their FPGA boards. Check out: ▶ DE2 http: //www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=30&PartNo=4 ▶ DE2-70 http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=183&No=226& PartNo=4 ▶ DE0-nano http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593& PartNo=4 The links are “hot”.
A low cost competitor There is actually quite a lot of competition. Boards similar to Terasic’s but using Xilinx parts can be found at http://Digilentinc.com. Xilinx is the dominant FPGA manufacturer. For example, the very low cost ($69 academic) BASYS2: From the Digilent web site.
Thoughts on DIY career development Once you graduate, career development likely will be mostly DIY. ▶ Buy an evaluation board. The Terasic DE2/DE2-70/DE0-Nano are great value. The Digilent Xilinx boards are also. I own two or more of each manufacturer’s. Do something with them! ▶ Find useful information. There’s a lot of useful material available on the web, and a lot that isn’t. Sorting can be a problem. The next slide lists some potential starter books.
Starting a personal library ▶ The SystemVerilog standard. Available from the library in e-form. ▶ FPGA prototyping by xxxxx examples: Xilinx Spartan-3 version / Pong P. Chu. Two versions, one where xxxxx is replaced by VHDL and the other by Verilog. I own the VHDL version.
