User manual

Metastability and mitigation
1EE Times-India | December 2007 | eetindia.com
By Saurabh Verma
Engineering Manager
Atrenta
Ashima S. Dabare
Consulting Applications Engineer
Atrenta
Introduction
SoCs are becoming more com-
plex these days. A lot of func-
tionality is being added to chips
and data is frequently transferred
from one clock domain to anoth-
er. Hence, clock domain crossing
verication has become one of
the major verication challenges
in deep submicron designs.
A clock domain crossing
occurs whenever data is trans-
ferred from a op driven by one
clock to a op driven by another
clock.
In Figure 1, signal A is
launched by the C1 clock do-
main and needs to be captured
properly by the C2 clock domain.
Depending on the relationship
between the two clocks, there
could be dierent types of prob-
lems in transferring data from
the source clock to the destina-
tion clock. Along with that, the
solutions to those problems can
also be dierent.
Traditional methods like
simulation and static timing
analysis alone are not sucient
to verify that the data is trans-
ferred consistently and reliably
across clock domains. Hence,
new verication methodologies
are required, but before devising
a new methodology it is impor-
tant to understand the issues re-
lated to clock domain crossings
properly. Dierent types of clock
domain crossings are discussed
here along with the possible is-
sues encountered in each one of
them and their solutions. A new
verication methodology is then
proposed which will ensure
that data is transferred correctly
across clock domains.
In all the subsequent sec-
tions, the signal names shown
in Figure 1 are directly used. For
example, C1 and C2 imply the
source and destination clocks re-
spectively. Similarly A and B are
used as source and destination
op outputs respectively. Also,
the source and destination ops
are assumed to be positive edge
triggered.
Clock Domain Crossing Issues
This section describes three main
issues, which can possibly occur
whenever there is a clock do-
main crossing. The solutions for
those issues are also described.
A. Metastability
Problem. If the transition on sig-
nal A happens very close to the
active edge of clock C2, it could
lead to setup or hold violation at
the destination op “FB”. As a re-
sult, the output signal B may os-
cillate for an indenite amount of
time. Thus the output is unstable
and may or may not settle down
to some stable value before the
next clock edge of C2 arrives. This
phenomenon is known as meta-
stability and the op “FB” is said to
have entered a metastable state.
Metastability in turn can have
the following consequences
from a design perspective:
1. If the unstable data is fed to
several other places in the
design, it may lead to a high
current ow and even chip
burnout in the worst case.
2. Dierent fan-out cones may
read dierent values of the
signal, and may cause the
design to enter into an un-
known functional state, lead-
ing to functional issues in the
design.
3. The destination domain out
-
put may settle down to the
new value or may return to
the old value. However, the
propagation delay could be
high leading to timing is-
sues.
For example, see Figure 2.
If the input signal A transitions
very close to the posedge of
clock C2, the output of the des-
tination op can be metastable.
As a result it can be unstable and
may nally settle to 1 or 0 as de-
picted by signals B1 and B2.
Solution. Metastability prob-
lems can be avoided by adding
special structures known as
synchronizers in the destination
domain. The synchronizers allow
sucient time for the oscilla-
tions to settle down and ensure
that a stable output is obtained
in the destination domain. A
commonly used synchronizer
is a multi-op synchronizer as
shown in Figure 3.
This structure is mainly used
for single and multi-bit control
signals and single bit data sig-
nals in the design. Other types
of synchronization schemes are
required for multi-bit data sig-
nals such as MUX recirculation,
handshake, and FIFO.
B. Data Loss
Problem. Whenever a new source
data is generated, the destination
Understanding clock domain
crossing issues
CloCks
1. Clock domain crossing
2. Metastability has consequences.
3. Multi-op synchronization.
▶
In theory, a flip-flop can take a very
long time to decide.
▶
It is not possible to guarantee that a
metastable state will not occur.
▶
Fast logic and slow clock rates help,
but . . . .
▶
It is possible to reduce the probability
of a metastable state to a very small
number.
▶
A two state synchronizer is often
adequate. However, for reliability
applications (e.g., aircraft control
systems) use three or more.
From: Understanding clock domain crossing issues, Saurabh.
EECS 452 – Fall 2014 Lecture 5 – Page 113/143 Tuesday – September 16, 2014