User manual

Metastability cause
clock a
clock b
Q
Q
setup time
hold time
t
s
t
h
clock b
X
X
▶
It takes time for things to get ready to happen and then to happen.
▶
If there isn’t adequate time, things go wrong.
▶
In theory, it can take a very long time to settle down.
▶
Metastability can be a problem in a FPGA’s clock distribution
network even in a single clock domain.
▶
Quartus II’s timing analyzer checks to whether or not the required
setup and hold times are met.
EECS 452 – Fall 2014 Lecture 5 – Page 114/143 Tuesday – September 16, 2014