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SPI timing example
B6
B7
SPI_CSn/SS
SPI_TX/MOSI
SPI_CLK/SCK
SPI_RX/MISO
B7
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
B6
B7
SPI_CSn/SS
SPI_TX/MOSI
SPI_CLK/SCK
SPI_RX/MISO
B7
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
B6
B7
SPI_CSn/SS
SPI_TX/MOSI
SPI_CLK/SCK
SPI_RX/MISO
B7
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
www.ti.com Serial Peripheral Interface Architecture
The clock polarity and phase can be specified through the CKPn and CKPHn bits of the SPI device
configuration register (SPIDC). You can program a different clock polarity and phase for each slave.
Table 2. Definition of SPI Modes
SPI Mode Clock Polarity Clock Phase
0 Active low (base value of clock is low) Data shifted out on the falling edge, input captured on the rising edge.
1 Active low (base value of clock is low) Data shifted out on the rising edge, input captured on the falling edge.
2 Active high (base value of clock is high) Data shifted out on the rising edge, input captured on the falling edge.
3 Active high (base value of clock is high) Data shifted out on the falling edge, input captured on the rising edge.
The timing diagrams for the four possible SPI modes are shown in Figure 4 through Figure 7. Please note
the following about these figures:
• Although the timing diagrams show an 8-bit character transfer, the character length can be set to 1
through 32 bits. The character length is selected with the CLEN bits SPICMD2.
• The number of characters transferred during one slave access is specified through the FLEN bits of
SPICMD1. The figures show the case of FLEN = 0 (1 character).
• The polarity of the chip select pins (SPI_CSn) can be configured through the CSPn bits of SPIDCR1
and SPIDCR2. The figures show a chip select polarity of active low.
• The SPI module automatically delays the first clock edge with respect to the activation of the SPI_CSn
pin by half a SPI_CLK cycle plus a system clock cycle. Additional clock delay cycles can be added
using the data delay bits (DDn) of SPIDCR1 and SPIDCR2. The figures below show the case of DDn =
0 (zero data delay) and CLKDV is odd.
Figure 4. SPI Mode 0 Transfer (CKPn = 0, CKPHn = 0)
Figure 5. SPI Mode 1 Transfer (CKPn = 0, CKPHn = 1)
Figure 6. SPI Mode 2 Transfer (CKPn = 1, CKPHn = 0)
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SPRUFO3–September 2009 Serial Peripheral Interface (SPI)
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SPICCR
SPICDR
Clock
Generator
SPIDCR1
SPIDCR2
SPICMD1
SPICMD2
Sequencer
SPISTAT1
SPISTAT2
SPIDAT2 SPIDAT1
SPI
Interruptto
CPU
SPI_CLK
SPI_CS
SPI_RX
SPI_TX
DSP
SPI_CLK
SPI_TX
SPI_RX
SPI_CSn
SPI-Compliant
Slave
SCK
MOSI
MISO
SS
Introduction www.ti.com
Figure 1. Serial Peripheral Interface (SPI) Block Diagram
1.4 Supported Use Case Statement
The SPI is intended for communication between the DSP and up to four SPI-complaint slave devices.
Typical applications include an interface to external I/O or peripheral expansion via devices such as shift
registers, display drivers, SPI EEPROMs, and analog-to-digital converters. The programmable
configuration capability of the SPI allows it to interface to a variety of SPI format devices without the need
for glue logic.
A typical SPI interface with a single slave device is shown in Figure 2. The DSP controls the flow of
communication by providing shift-clock (SPI_CLK) and slave-select signals (SPI_CSn).
Figure 2. Typical SPI Interface
1.5 Industry Standard(s) Compliance Statement
The SPI does not conform to a specific industry standard.
10
Serial Peripheral Interface (SPI) SPRUFO3–September 2009
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▶
C5515 SPI mode 2 is shown.
▶
The TI C5515 SPI can only be a master!
▶
We can design either master or slave
interfaces in the FPGA.
From TI’s SPRUFO3.pdf.
EECS 452 – Fall 2014 Lecture 5 – Page 119/143 Tuesday – September 16, 2014