User manual

Synchronizer module
// File name: synchronizer.sv
//
// 09Aug2012 .. version started .. K.Metzger
//
module synchronizer
(
input signal_in,
input clear_in,
output signal_out,
input clk);
logic [1:0] delay;
assign signal_out = delay[1];
always_ff@(posedge(clk), posedge(clear_in)) begin
if (clear_in) delay <= 0;
else delay <= {delay[0], signal_in};
end
endmodule
EECS 452 – Fall 2014 Lecture 5 – Page 129/143 Tuesday – September 16, 2014