User manual

How to make the D/A work
Here are some observations/guesses about control of the D/A. These
are based on the timing timing diagram and written signal
descriptions contained in the data sheet. Use of a state machine in the
D/A control logic is assumed.
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sync_n can remain high between updates going low when a serial
transfer is to start.
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The start of a serial transfer is detected by sampling sync_n
using the rising edges of sclk.
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Data bits are sampled on the falling edges of sclk.
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There is a counter in the D/A that loads D/A holding register
from the input shift register. Possibly on the 16th falling edge of
sclk.
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After loading the DAC register the state machine waits for the
next high to low transition on sync_n
EECS 452 – Fall 2014 Lecture 5 – Page 132/143 Tuesday – September 16, 2014