User manual

M4K RAM
Off-fabric.
250 MHz max clock.
4608 bits (inc. parity).
4K×1
2K×2
1K×4
512×8
512×9
256×16
256×18
128×32 (not avail. true dual)
128×36 (not avail. true dual)
Table 2–7. M4K Memory Modes
Memory Mode Description
Single-port memory M4K blocks support single-port mode, used when
simultaneous reads and writes are not required.
Single-port memory supports non-simultaneous
reads and writes.
Simple dual-port memory Simple dual-port memory supports a
simultaneous read and write.
Simple dual-port with mixed
width
Simple dual-port memory mode with different
read and write port widths.
True dual-port memory True dual-port mode supports any combination of
two-port operations: two reads, two writes, or one
read and one write at two different clock
frequencies.
True dual-port with mixed
width
True dual-port mode with different read and write
port widths.
Embedded shift register M4K memory blocks are used to implement shift
registers. Data is written into each address
location at the falling edge of the clock and read
from the address at the rising edge of the clock.
ROM The M4K memory blocks support ROM mode. A
MIF initializes the ROM contents of these blocks.
FIFO buffers A single clock or dual clock FIFO may be
implemented in the M4K blocks. Simultaneous
read and write from an empty FIFO buffer is not
supported.
From Cyclone II documentation.
EECS 452 – Fall 2014 Lecture 5 – Page 15/143 Tuesday – September 16, 2014