User manual

Comments on (System) Verilog references

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I’ve seen the claim (on the web) that the SystemVerilog standard

makes a good tutorial. With a bit of caution, I have found the

standard to be very useful. Having a previous bit of Verilog

background helps deciding what to pay attention to and what to

skip over.

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There don’t seem to be many texts focused on design and synthesis

using SystemVerilog. There are several that focus on the use of

SystemVerilog for design veriﬁcation and benchmarking.

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I used Mark Zwolinski’s Digital System Design with SystemVerilog as

as a reference for my learning. This is well written and reasonably

EECS 452 – Fall 2014 Lecture 5 – Page 31/143 Tuesday – September 16, 2014