User manual

Verilog DIY learning links
http://www.asic-world.com, in particular:
http://www.asic-world.com/verilog/verilog_one_day.html
Altera’s HDL design examples:
http://www.altera.com/support/examples/exm-index.html
How does SystemVerilog extend Verilog?
http://en.wikipedia.org/wiki/SystemVerilog
There are also two EECS 270 tutorials linked to on the lab exercise 3
write-up.
Consider using SystemVerilog.
EECS 452 – Fall 2014 Lecture 5 – Page 33/143 Tuesday – September 16, 2014