User manual

Processing a design
A Verilog design description describes the
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The registers making up a device.
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The interconnections between registers.
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The timing of changes in the register states.
A series of Quartus programs
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synthesizes the design to the basic logic element level.
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fits the result into the FPGA and routes signals.
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generates a .sof file to be used to configure the logic elements and
establish routing segments and .pof file for possible use in
programming the boot EPROM.
The loader program is used to download the .sof file into the FPGA and
start it running.
Note: For the DE0-Nano a .pof is not generated and the .sof file needs
to be further processed to get the boot EPROM contents.
EECS 452 – Fall 2014 Lecture 5 – Page 36/143 Tuesday – September 16, 2014