User manual

It remains to . . .
▶
Import a .qsf file. This maps pins on the FPGA to name
space. These can vary depending on the board and where you
got the file from.
▶
Remove a pin conflict between a pin that is connected to a
slide switch and Quartus defaults as a programming pin. This
likely is already done in the .qsf file used in the lab.
▶
Probably should supply an .sdc file to define the clocking.
This enables the timing analyzer to check for proper set-up
and hold times. This is often skipped when doing simple
small projects.
EECS 452 – Fall 2014 Lecture 5 – Page 48/143 Tuesday – September 16, 2014