User manual

Comments on module structure
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(System)Verilog is very C like.
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Multiple modules can be present in a source file.
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Consider naming the top module with the project name
followed by _top. For example my VGA_nano project top file
is named VGA_nano_top.sv.
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The top level module port signal names need to match the
names in the assigned .qsf file. The .qsf file assigns signal
names to actual pins on the FPGA.
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Occasionally one wants to combine two existing projects each
having its own top file. Consider using a top_top file.
EECS 452 – Fall 2014 Lecture 5 – Page 52/143 Tuesday – September 16, 2014