User manual

Altera’s addsub.v example
module addsub
(
input [7:0] dataa,
input [7:0] datab,
input add_sub, // if this is 1, add; else subtract
input clk,
output reg [8:0] result
);
always @ (posedge clk)
begin
if (add_sub)
result <= dataa + datab;
else
result <= dataa - datab;
end
endmodule
This is a behavioral description of what is to be accomplished. Note the
automatic promotion of the number of bits.
EECS 452 – Fall 2014 Lecture 5 – Page 55/143 Tuesday – September 16, 2014