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Verilog’s operators
The point of the next three slides is to make you aware of the
operators available in Verilog.
These generally cause the required logic to be synthesized. For
example, if we have two 16-bit reg items we can add them
together and place the result in a third (which might be one of the
two original) by writing:
a <= b+c;
Verilog takes on the responsibility of supplying the needed adder
logic. Each time we write an expression like this we create another
adder.
EECS 452 – Fall 2014 Lecture 5 – Page 61/143 Tuesday – September 16, 2014