User manual

Verilog’s operator precedences
Table 11-2—Operator precedence and associativity
Operator Associativity Precedence
() [] :: . left highest
+ - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary)
** left
* / % left
+ - (binary) left
<< >> <<< >>> left
< <= > >= inside dist left
== != === !== ==? !=? left
& (binary) left
^ ~^ ^~ (binary) left
| (binary) left
&& left
|| left
?: (conditional operator) right
–> <-> right
= += -= *= /= %= &= ^= |=
<<= >>= <<<= >>>= := :/ <=
none
{} {{}} concatenation lowest
From IEEE Standard 1800-2009.
EECS 452 – Fall 2014 Lecture 5 – Page 64/143 Tuesday – September 16, 2014