User manual

SystemVerilog’s data types
In Verilog there are two primary data types, wires (wire) and
registers(reg).
Wires represent connections. Registers correspond to variables to
hold values.
The default data type is a one bit wide wire.
Note: registers are not necessarily actual registers.
SystemVerilog introduced logic type to replace the use of wire
and reg.
SystemVerilog is a weakly typed language.
EECS 452 – Fall 2014 Lecture 5 – Page 65/143 Tuesday – September 16, 2014