User manual

Unrestricting the signal order
The order of the signals in the instantiation of a module normally MUST
match the order in the associated module definition.
For modules having a large of number of signals to connect this can be a
recipe for disaster.
Today’s common wisdom is that having to match order is not a good
thing. That is, one should not require it.
Using the construct shown in the FullAdder_B1 instantiation removes
the matching order requirement. The signal order used in this
instantiation is the reverse of that of the module definition, yet, the logic
works.
FullAdder_B1 (.cout(oLEDR[9]), .sum(oLEDR[8]),
.cin(iSW[0]), .b(iSW[2]), .a(iSW[1])
);
Quartus II makes the external signal connections to the top module by
name.
EECS 452 – Fall 2014 Lecture 5 – Page 69/143 Tuesday – September 16, 2014