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Implementing a DDS sine table
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Use a case statement with assignments. Simple and easy. This is one
of ways described in the lab exercise. A large table requires use of a
lot of logic elements. A 256 × 16 table uses 4096 LE D-registers.
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Indexed arrays are supported by Verilog 2001. These can be
initialized by reading an external initialization file (constructs exist
to do this) or by using an initial block.
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SystemVerilog allows array initialization values to be listed pretty
much as in the same manner as for C.
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Use a M4K memory block to hold the table. Off fabric. Simply a RAM
block initialized using a .mif file. If you never write to it, initialized
RAM serves as a ROM. A single M4K memory block can hold a
256 × 16 sine table with 512 (nominally parity) bits left over.
EECS 452 – Fall 2014 Lecture 5 – Page 83/143 Tuesday – September 16, 2014