User manual

Sine generation using a case statement
always@(negedge clock)
counter <= counter + FTV;
always@
*
begin
case(counter[9:6])
0 : dataOut <= 0;
1 : dataOut <= 12539;
2 : dataOut <= 23170;
3 : dataOut <= 30273;
4 : dataOut <= 32767;
5 : dataOut <= 30273;
6 : dataOut <= 23170;
7 : dataOut <= 12539;
8 : dataOut <= 0;
9 : dataOut <= -12539;
10 : dataOut <= -23170;
11 : dataOut <= -30273;
12 : dataOut <= -32767;
13 : dataOut <= -30273;
14 : dataOut <= -23170;
15 : dataOut <= -12539;
default :
dataOut <= 0 ;
endcase
end
EECS 452 – Fall 2014 Lecture 5 – Page 84/143 Tuesday – September 16, 2014