User manual

Verilog multiplication and Cyclone II

In Exercise 3 a multiplication is involved in computing FTVs. At the

Verilog level one can write assign out = a

b. What’s behind the

implementation?

Using Google the following two documents were found:

▶

Recommended HDL Coding Styles.

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Embedded Multipliers in Cyclone II Devices.

Figure 12–2. Multiplier Block Architecture

CLRN

D Q

ENA

Data A

Data B

aclr

clock

ena

signa

(1)

signb

(1)

CLRN

D Q

ENA

CLRN

D Q

ENA

Data Out

Embedded Multiplier Block

Output

Input

Example 11–1. Verilog HDL Unsigned Multiplier

module unsigned_mult (out, a, b);

output [15:0] out;

input [7:0] a;

input [7:0] b;

assign out = a * b;

endmodule

From Altera documentation.

EECS 452 – Fall 2014 Lecture 5 – Page 94/143 Tuesday – September 16, 2014