User manual

Blinky comments
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A common problem is mismatching the top level signal names with the
ones used in the .qsf file. This is NOT flagged as an error!
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What happens to led_bit when counter is not 0? A latch is synthesized.
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The values of led_bit and counter change only on the positive edge
transition of clk.
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25 bits allows counts of up to 33,554,432.
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One of my SystemVerilog fantasies is that counting down to 0 simplifies the
end test logic.
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SystemVerilog is a weakly typed language. It allows to do things like take an
integer and put it into a register. The value 25000000-1 is evaluated as a 32
bit value, truncated to 25 bits and then converted into a logic vector that
can be loaded into a 25 bit register.
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This is all well and good if I wrote code to do what I intended. If not, then
the compiler does it’s best to figure out what I meant and doesn’t tell me
what it did.
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It is very important to say you mean and mean what you say.
EECS 452 – Fall 2014 Lecture 5 – Page 98/143 Tuesday – September 16, 2014