Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT OF FOR THE DEGREE IN Bachelor of Technology In Electronics and Communication Engineering By Sahil Sharma Roll no. 10609026 Anupam pal Roll No.
NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA CERTIFICATE This is to certify that the thesis entitled, “Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit “submitted by Anupam Pal and Sahil Sharma in partial fulfillment of the requirements for the award of Bachelor of Technology Degree in Electronics and communication at National Institute of Technology, Rourkela (Deemed University), is an authentic work carried out by them under my supervision.
ACKNOWLEDGEMENT I avail this opportunity to extent my hearty indebtedness to my guide “Prof. S.K. Patra”, Electronics And Communication Engineering Department, for his valuable guidance, constant encouragement and kind help at different stages for the execution of this dissertation work. I want to thank all my teachers Prof. G.S. Rath, Prof. K. K. Mahapatra, And Prof. S. Meher for providing a solid background for my studies.
Contents SI. No. Topic Page No. 1. Chapter 1: Introduction 5-12 2. Chapter 2: Literature review 13-14 3. Chapter 3: Methodology and problem formulation 15-30 4. Chapter 4: Result and Discussions 31-32 5.
ABSTRACT A web server is a computer program that delivers (serves) content, such as web pages, to the Clients. A field-programmable gate array (FPGA) is an integrated circuit designed to be Configured by the customer or designer. We are aiming at implementing a web server using the FPGA development board (DE 270). Implementation of web server can be done by first instantiating a Nios II system in the board.
INTRODUCTION CHAPTER 1
Introduction: FPGA & Altera’s DE270 FPGA Development Board A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing ,hence called field-programmable. The FPGA configuration is generally specified using a hardware description language(HDL). FPGAs can be used to implement any logical function.
Quartus II Quartus II is a CAD system used to implement circuits in an Altera FPGA device. The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system. The desired circuit can be entered in block diagram form(schematic) or using hardware description language like VHDL or Verilog.
The CAD flow involves the following steps: Design Entry – the desired circuit is specified either by means of a schematic diagram, or by using a hardware description language, such as Verilog or VHDL.
We have used VHDL to enter the design in Quartus II. The entered circuit is compiled to generate the SRAM object file(.sof) needed to configure the FPGA. After compiling the circuit is then simulated to check the functionality of the circuit using a test vector. The simulated circuit is then configured into the FPGA chip to actually implement the circuit. Programming and Configuring the FPGA Device The FPGA device must be programmed and configured to implement the designed circuit.
SOPC Builder Altera’s Nios II is a soft processor is defined in a hardware description language. It can be implemented in Altera’s FPGA devices by using the Quartus II CAD system. To implement a useful system it is necessary to add other functional units such as memories, input/output interfaces, timers, and communications interfaces. To facilitate the implementation of such systems, it is useful to have computer-aided-design (CAD) software for implementing a systemon-a-programmable-chip (SOPC).
• Examine a graphical view of an instruction trace that records the set of recently executed instructions. • Perform terminal input/output via the JTAG UART component.
LITERATURE REVIEW CHAPTER 2
Literature Review: FPGA development kits are generally used for basic logic implementations. Previously for web servers, computers were used that used to run some application program. For small purpose web servers, the processing power of a full fledged computer is not used efficiently. By implementing a system on a programmable chip, we are implementing a reduced instruction set computer(RISC).
METHODOLOGY AND PROBLEM FORMULATION CHAPTER 3
3.
The Nios II processor and the interfaces needed to connect to other chips on the DE2 board are implemented in the Cyclone II FPGA chip. These components are interconnected by means of the interconnection network called the Avalon Switch Fabric. The memory blocks in the Cyclone II device can be used to provide an on-chip memory for the Nios II processor. The SRAM, SDRAM and Flash memory chips on the DE2 board are accessed through the appropriate interfaces.
3.2 Design Flow: SOPC builder tool of the Quartus II software is used for implementing the Nios II System. The different specifications for defining the system are as follows: Clock: 50 Mhz, External Device Type: Cyclone II Processor: Nios II/e which is the simplest version of the processor is used for our application.
Parallel Input Output(I): Width: 8 bits Direction: input ports only Parallel Input Output(II): Width: 8 bits Direction: output ports only JTAG UART: We wish to connect to a host computer and provide a means for communication between the Nios II system and the host computer.
Having specified all components needed to implement the desired system, it can now be generated. Select the System Generation tab.Turn off Simulation – Create simulator project files, because we will not deal with the simulation of hardware. Click Generate on the bottom of the SOPC Builder window. The generation process produces the messages displayed in the figure. When SYSTEMGENERATION COMPLETED" appears.
3.3 Integration of the Nios II System into a Quartus II Project To complete the hardware design, we have to perform the following: • Instantiate the module generated by the SOPC Builder into the Quartus II project. • Assign the FPGA pins. • Compile the designed circuit. • Program and configure the Cyclone II device on the DE2 board. 3.3.
The VHDL code produced by the SOPC is quite large. The portion of code that defines port signals for entity nios_system is shown as: entity nios_system is port( --1) global signals signal clk : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; --2) LEDs signal out_port_from _the_LEDs : OUT STD_LOGIC_VECTOR(7 DOWN TO 0); signal in_from_the_switches : IN STD_LOGIC_VECTOR(7 DOWN TO 0); ); end entity nios_system; The 8-bit vector that is the input to the parallel port Switches is called in_port_to_the_Switches.
3.3.2 A top-level VHDL entity that instantiates the Nios II system(for light control circuit): −− Implements a simple Nios II system for the DE2 board. −− Inputs: SW7−0 are parallel port inputs to the Nios II system −− CLOCK_50 is the system clock −− KEY0 is the active-low system reset −− Outputs: LEDG7−0 are parallel port outputs from the Nios II system LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.
END lights; ARCHITECTURE Structure OF lights IS COMPONENT nios_system PORT ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; out_port_from_the_LEDs : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); in_port_to_the_Switches : IN STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN −− Instantiate the Nios II system entity generated by the SOPC Builder NiosII: nios_system PORT MAP (CLOCK_50, KEY(0), LEDG, SW); END Structure;
3.3.3 Compiling the generated code along with top level VHDL entity: Add this file and all the *.vhd files produced by the SOPC Builder to your Quartus II project. Also, add the necessary pin assignments on the DE2 board to your project. Pin assignments are made by importing the assignments given in the file called DE2_pin_assignments.csv in the directory DE2_tutorials\design_files, which is included on the CD-ROM that accompanies the DE2 board and can also be found on Altera’s DE2 web pages.
4. The configuration file lights.sof should be listed in the window. If the file is not already listed, then add this file. 5. Click the box under Program/Configure and press start to configure the FPGA.
3.5 Running the Application Program: Having configured the required hardware in the FPGA device, it is now necessary to create and execute an application program that performs the desired operation. This can be done by writing the required program either in the Nios II assembly language or in a high-level language such as C. A Nios II assembly-language program that implements the trivial task of light control circuit is shown as: .include "nios_macros.s" .equ Switches, 0x00001800 .equ LEDs, 0x00001810 .
The program loads the addresses of the Data registers in the two PIOs into processor registers r2 and r3. It then has an infinite loop that merely transfers the data from the input PIO, Switches, to the output PIO, LEDs. The program includes the assembler directive .include "nios_macros.s" which informs the Assembler to use the Nios II macros that specify how the movia pseudoinstructions can be assembled. The directive .
This software needs to know the characteristics of the designed Nios II system, which are given in the ptf file nios_system.ptf. Click the Nios II >Configure system... menu item to display the Nios II System Configuration window and perform the following steps: 1. Select the USB-Blaster cable from the Cable drop-down list, which is used with DE2 board. 2. Click Browse... to display a file selection window and choose the nios_system.ptf file. Note that this file is in the design directory sopc_builder_tutorial.
3.6.1 Compiling and loading the program: After successfully creating a project, the program can be compiled and downloaded onto the DE2 board. There are three different commands that can be used to compile and/or load a program: • Actions > Compile menu item or toolbar button: Compiles the source files into an ELF and SREC file. The generated ELF and SREC files are placed in the project’s directory.
RESULT and DISCUSSIONS CHAPTER 4
Result and Discussions: The Nios II system was programmed and configured in the board successfully. This system can now be developed for any desired application. We developed the system for a simple light control system. The system can be developed to be used as web server by edditng the top level VHDL entity and running a suitable application program in the system. This is controlled and monitored by the altera debug client software.
References
References: [1] www.altera.com › Products › Literature. [2]www.smdp.iitkgp.ernet.in/PDF%5CVLSI_DSP%5CEmbedded_System_Desig n.pdf. [3] http://www.nioswiki.com/Cyclone_III_-_Nios_II_-_Starter_board [4] http://www.alteraforum.com/ [5] www.wikipedia.org.