Specifications

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We have used VHDL to enter the design in Quartus II. The entered circuit is compiled to generate the
SRAM object file(.sof) needed to configure the FPGA. After compiling the circuit is then simulated to
check the functionality of the circuit using a test vector. The simulated circuit is then configured into the
FPGA chip to actually implement the circuit.
Programming and Configuring the FPGA Device
The FPGA device must be programmed and configured to implement the designed circuit. The
required configuration file is generated by the Quartus II Compiler’s Assembler module. Altera’s
DE2 board allows the configuration to be done in two different ways, known as JTAG and AS
modes. The configuration data is transferred from the host computer (which runs the Quartus II
software) to the board by means of a cable that connects a USB port on the host computer to
the leftmost USB connector on the board.
In the JTAG mode, the configuration data is loaded directly into the FPGA device. The acronym
JTAG stands for Joint Test Action Group. This group defined a simple way for testing digital
circuits and loading data into them, which became an IEEE standard. If the FPGA is configured
in this manner, it will retain its configuration as long as the power remains turned on. The
configuration information is lost when the power is turned off. The second possibility is to use
the Active Serial (AS) mode. In this case, a configuration device that includes some flash
memory is used to store the configuration data. Quartus II software places the configuration
data into the configuration device on the DE2 board. Then, this data is loaded into the FPGA
upon power-up or reconfiguration. Thus, the FPGA need not be configured by the Quartus II
software if the power is turned off and on. The choice between the two modes is made by the
RUN/PROG switch on the DE2 board. The RUN position selects the JTAG mode, while the
PROG position selects the AS mode.