Specifications

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The Nios II processor and the interfaces needed to connect to other chips on the DE2 board are
implemented in the Cyclone II FPGA chip. These components are interconnected by means of
the interconnection network called the Avalon Switch Fabric. The memory blocks in the Cyclone
II device can be used to provide an on-chip memory for the Nios II processor. The SRAM,
SDRAM and Flash memory chips on the DE2 board are accessed through the appropriate
interfaces. Parallel and serial input/output interfaces provide typical I/O ports used in computer
systems. A special JTAG UART interface is used to connect to the circuitry that provides a
Universal Serial Bus (USB) link to the host computer to which the DE2 board is connected. This
circuitry and the associated software is called the USB-Blaster. Another module, called the
JTAG Debug module, is provided to allow the host computer to control the Nios II system. It
makes it possible to perform operations such as downloading programs into memory, starting
and stopping execution, setting breakpoints, and collecting real-time execution trace data. Since
all parts of the Nios II system implemented on the FPGA chip are defined by using a hardware
description language, a knowledgeable user could write such code to implement any part of the
system. This would be an onnerous and time consuming task. Instead, one can use the SOPC
Builder to implement a desired system simply by choosing the required components and
specifying the parameters needed to make each component fit the overall requirements of the
system. In this tutorial, we will illustrate the capability of the SOPC Builder by designing a very
simple system. The same approach is used to design large systems.