Specifications

19
Parallel Input Output(I):
Width: 8 bits
Direction: input ports only
Parallel Input Output(II):
Width: 8 bits
Direction: output ports only
JTAG UART:
We wish to connect to a host computer and provide a means for communication between the
Nios II system and the host computer. This can be accomplished by instantiating the JTAG
UART interface as follows:
Write FIFO:
Depth: 64 bits
Read FIFO:
Depth: 64 bits
After specifying these components for the Nios II system, the following flow is followed:
 The base and end addresses of the various components in the designed system can be
assigned by the user, but they can also be assigned automatically by the SOPC Builder.
We will choose the latter possibility. So, select the command (using the menus at the top
of the SOPC Builder window) System > Auto-Assign Base Addresses, which produces
the assignment.