Specifications

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3.3.2 A top-level VHDL entity that instantiates the Nios II system(for light control
circuit):
−− Implements a simple Nios II system for the DE2 board.
−− Inputs: SW7−0 are parallel port inputs to the Nios II system
−− CLOCK_50 is the system clock
−− KEY0 is the active-low system reset
−− Outputs: LEDG7−0 are parallel port outputs from the Nios II system
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY lights IS
PORT (
SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
CLOCK_50 : IN STD_LOGIC;
LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);