Specifications

9
The CAD flow involves the following steps:
Design Entry – the desired circuit is specified either by means of a schematic diagram, or by using a
hardware description language, such as Verilog or VHDL.
Synthesis – the entered design is synthesized into a circuit that consists of the logic elements (LEs)
provided in the FPGA chip
Functional Simulation – the synthesized circuit is tested to verify its functional correctness; this
simulation does not take into account any timing issues
Fitting – the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in
an actual FPGA chip; it also chooses routing wires in the chip to make the required connections between
specific LEs.
Timing Analysis – propagation delays along the various paths in the fitted circuit are analyzed to provide
an indication of the expected performance of the circuit.
Timing Simulation – the fitted circuit is tested to verify both its functional correctness and timing
Programming and Configuration – the designed circuit is implemented in a physical FPGA chip by pro-
gramming the configuration switches that configure the LEs and establish the required wiring
connections.