Altera DE2 Board DE2 Development and Education Board User Manual Version 1.
Altera DE2 Board CONTENTS Chapter 1 DE2 Package.....................................................................................................................1 1.1 1.2 1.3 Package Contents .................................................................................................................1 The DE2 Board Assembly....................................................................................................2 Getting Help................................................................
Altera DE2 Board 5.2 5.3 TV Box Demonstration ......................................................................................................55 USB Paintbrush..................................................................................................................57 5.4 5.5 5.6 USB Device........................................................................................................................59 A Karaoke Machine ................................................................
DE2 User Manual Chapter 1 DE2 Package The DE2 package contains all components needed to use the DE2 board in conjunction with a computer that runs the Microsoft Windows software. 1.1 Package Contents Figure 1.1 shows a photograph of the DE2 package. Figure 1.1. The DE2 package contents.
DE2 User Manual The DE2 package includes: • • DE2 board USB Cable for FPGA programming and control • CD-ROM containing the DE2 documentation and supporting materials, including the User Manual, the Control Panel utility, reference designs and demonstrations, device datasheets, tutorials, and a set of laboratory exercises • CD-ROMs containing Altera’s Quartus® II Web Edition and the Nios® II Embedded Design Suit Evaluation Edition software.
DE2 User Manual 1.3 Getting Help Here are the addresses where you can get help if you encounter problems: • Altera Corporation 101 Innovation Drive San Jose, California, 95134 USA Email: university@altera.com • Terasic Technologies No. 356, Sec. 1, Fusing E. Rd. Jhubei City, HsinChu County, Taiwan, 302 Email: support@terasic.com Web: DE2.terasic.com • Arches Computing Unit 708-222 Spadina Ave Toronto, Ontario, Canada M5T3A2 Email: DE2support@archescomputing.com Web: DE2.archescomputing.
DE2 User Manual Chapter 2 Altera DE2 Board This chapter presents the features and design characteristics of the DE2 board. 2.1 Layout and Components A photograph of the DE2 board is shown in Figure 2.1. It depicts the layout of the board and indicates the location of the connectors and key components. Figure 2.1. The DE2 board. The DE2 board has many features that allow the user to implement a wide range of designed circuits, from simple circuits to various multimedia projects.
DE2 User Manual • • • 4-Mbyte Flash memory (1 Mbyte on some boards) SD Card socket 4 pushbutton switches • • • • 18 toggle switches 18 red user LEDs 9 green user LEDs 50-MHz oscillator and 27-MHz oscillator for clock sources • • • • 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks VGA DAC (10-bit high-speed triple DACs) with VGA-out connector TV Decoder (NTSC/PAL) and TV-in connector 10/100 Ethernet Controller with a connector • • • USB Host/Slave Controller with USB typ
DE2 User Manual Figure 2.2. Block diagram of the DE2 board. Following is more detailed information about the blocks in Figure 2.
DE2 User Manual SRAM • 512-Kbyte Static RAM memory chip • • Organized as 256K x 16 bits Accessible as memory for the Nios II processor and by the DE2 Control Panel SDRAM • • • 8-Mbyte Single Data Rate Synchronous Dynamic RAM memory chip Organized as 1M x 16 bits x 4 banks Accessible as memory for the Nios II processor and by the DE2 Control Panel Flash memory • • • 4-Mbyte NOR Flash memory (1 Mbyte on some boards) 8-bit data bus Accessible as memory for the Nios II processor and by the DE2 Control P
DE2 User Manual Audio CODEC • Wolfson WM8731 24-bit sigma-delta audio CODEC • • • Line-level input, line-level output, and microphone input jacks Sampling frequency: 8 to 96 KHz Applications for MP3 players and recorders, PDAs, smart phones, voice recorders, etc.
DE2 User Manual Serial ports • • • • One RS-232 port One PS/2 port DB-9 serial connector for the RS-232 port PS/2 connector for connecting a PS2 mouse or keyboard to the DE2 board IrDA transceiver • • Contains a 115.
DE2 User Manual At this point you should observe the following: • All user LEDs are flashing • • • • All 7-segment displays are cycling through the numbers 0 to F The LCD display shows Welcome to the Altera DE2 Board The VGA monitor displays the image shown in Figure 2.3.
DE2 User Manual Chapter 3 DE2 Control Panel The DE2 board comes with a Control Panel facility that allows a user to access various components on the board through a USB connection from a host computer. This chapter first presents some basic functions of the Control Panel, then describes its structure in block diagram form, and finally describes its capabilities. 3.
DE2 User Manual 7. The Control Panel is now ready for use; experiment by setting the value of some 7-segment display and observing the result on the DE2 board. Figure 3.1. Quartus II Programmer window. Figure 3.2. The DE2 Control Panel. The concept of the DE2 Control Panel is illustrated in Figure 3.3. The IP that performs the control functions is implemented in the FPGA device. It communicates with the Control Panel window, which is active on the host computer, via the USB Blaster link.
DE2 User Manual Figure 3.3. The DE2 Control Panel concept. The DE2 Control Panel can be used to change the values displayed on 7-segment displays, light up LEDs, talk to the PS/2 keyboard, read/write the SRAM, Flash Memory and SDRAM, load an image pattern to display as VGA output, load music to the memory and play music via the audio DAC.
DE2 User Manual Figure 3.4. 3.3 Controlling LEDs and the LCD display. SDRAM/SRAM Controller and Programmer The Control Panel can be used to write/read data to/from the SDRAM and SRAM chips on the DE2 board. We will describe how the SDRAM may be accessed; the same approach is used to access the SRAM. Click on the SDRAM tab to reach the window in Figure 3.5. Figure 3.5. Accessing the SDRAM.
DE2 User Manual A 16-bit word can be written into the SDRAM by entering the address of the desired location, specifying the data to be written, and pressing the Write button. Contents of the location can be read by pressing the Read button. Figure 3.5 depicts the result of writing the hexadecimal value 6CA into location 200, followed by reading the same location. The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows: 1.
DE2 User Manual 3.4 Flash Memory Programmer The Control Panel can be used to write/read data to/from the Flash memory chip on the DE2 board. It can be used to: • • • Erase the entire Flash memory Write one byte to the memory Read one byte from the memory • • Write a binary file to the memory Load the contents of the Flash memory into a file Note the following characteristics of the Flash memory: • • The Flash memory chip is organized as 4 M (or 1 M on some boards) x 8 bits.
DE2 User Manual 2. Enter the desired address into the Address box and the data byte into the wDATA box. Then, click on the Write button. To read a byte of data from a random location, enter the address of the location and click on the Read button. The rDATA box will display the data read back from the address specified. The Sequential Write function is used to load a file into the Flash chip as follows: 1. Specify the starting address and the length of data (in bytes) to be written into the Flash memory.
DE2 User Manual II chip. The connection between the Audio DAC Controller and a lookup table in the FPGA is used to produce a test audio signal of 1 kHz. To let users implement and test their IP cores (written in Verilog) without requiring them to implement complex API/Host control software and memory (SRAM/SDRAM/Flash) controllers, we provide an integrated control environment consisting of a software controller in C++, a USB command controller, and a multi-port SRAM/SDRAM/Flash controller. Figure 3.7.
DE2 User Manual 3.6 TOOLS – Multi-Port SRAM/SDRAM/Flash Controller The TOOLS page of the Control Panel GUI allows selection of the User Ports. We will illustrate a typical process by implementing a Flash Music Player. The music data is loaded into the Flash memory. User Port 1 in the Flash Controller is used to send the music data to the Audio DAC Controller and hence to the audio output jack. You can implement this application as follows: 1. Erase the Flash memory (as explained in Section 3.4).
DE2 User Manual AUDIO_DAC Verilog module defines a circuit that reads the contents of the Flash memory and sends it to the external audio chip. 3.7 VGA Display Control The Control Panel provides a tool with the associated IP that allows the user to display an image via the VGA output port. To illustrate this feature, we will show how an image can be displayed on a VGA monitor.
DE2 User Manual • Select the TOOLS page and choose Asynchronous 1 for the SRAM multiplexer port as shown in Figure 3.10. Click on the Configure button to activate the multi-port setup. Figure 3.10. Use the Asynchronous Port 1 to access the image data in the SRAM. • • The FPGA is now configured as indicated in Figure 3.11. Select the VGA page and deselect the checkbox Default Image. • The VGA monitor should display the picture.dat image from the SRAM, as depicted in Figure 3.12.
DE2 User Manual Figure 3.12. A displayed image. You can display any image file by loading it into the SRAM chip or into an M4K memory block in the Cyclone II chip. This requires generating a bitmap file, which may be done as follows: 1. Load the desired image into an image processing tool, such as Corel PhotoPaint. 2. Resample the original image to have a 640 x 480 resolution. Save the modified image in the Windows Bitmap format. 3. Execute DE2_control_panel\ImgConv.
DE2 User Manual Figure 3.13. The image converter window. Image Source R/G/B Filter Band B&W Threshold Filter Output Result (640x480) Color Picture R/G/B N/A Color Picture R/G/B (optional) BW Threshold Raw_Data_BW + Raw_Data_BW.txt Grayscale N/A N/A N/A BW Threshold Raw_Data_BW + Raw_Data_Gray Raw_Data_Gray Picture Grayscale Picture Raw_Data_BW.txt Note: Raw_Data_BW.txt is in MIF/Intel Hex format and ready to be stored in an M4K SRAM.
DE2 User Manual Chapter 4 Using the DE2 Board This chapter gives instructions for using the DE2 board and describes each of its I/O devices. 4.1 Configuring the Cyclone II FPGA The procedure for downloading a circuit from a host computer to the DE2 board is described in the tutorial Quartus II Introduction. This tutorial is found in the DE2_tutorials folder on the DE2 System CD-ROM, and it is also available on the Altera DE2 web pages.
DE2 User Manual Configuring the FPGA in JTAG Mode Figure 4.1 illustrates the JTAG configuration setup. To download a configuration bit stream into the Cyclone II FPGA, perform the following steps: • • • Ensure that power is applied to the DE2 board Connect the supplied USB cable to the USB Blaster port on the DE2 board (see Figure 2.1) Configure the JTAG programming circuit by setting the RUN/PROG switch (on the left side of the board) to the RUN position.
DE2 User Manual Figure 4.2. The AS configuration scheme. In addition to its use for JTAG and AS programming, the USB Blaster port on the DE2 board can also be used to control some of the board's features remotely from a host computer. Details that describe this method of using the USB Blaster port are given in Chapter 3. 4.2 Using the LEDs and Switches The DE2 board provides four pushbutton switches. Each of these switches is debounced using a Schmitt Trigger circuit, as indicated in Figure 4.3.
DE2 User Manual There are 27 user-controllable LEDs on the DE2 board. Eighteen red LEDs are situated above the 18 toggle switches, and eight green LEDs are found above the pushbutton switches (the 9th green LED is in the middle of the 7-segment displays). Each LED is driven directly by a pin on the Cyclone II FPGA; driving its associated pin to a high logic level turns the LED on, and driving the pin low turns it off. A schematic diagram that shows the pushbutton and toggle switches is given in Figure 4.4.
DE2 User Manual Figure 4.5. Schematic diagram of the LEDs. Signal Name FPGA Pin No.
DE2 User Manual Signal Name FPGA Pin No. Description KEY[0] PIN_G26 Pushbutton[0] KEY[1] PIN_N23 Pushbutton[1] KEY[2] PIN_P23 Pushbutton[2] KEY[3] PIN_W26 Pushbutton[3] Table 4.2. Pin assignments for the pushbutton switches. Signal Name FPGA Pin No.
DE2 User Manual 4.3 Using the 7-segment Displays The DE2 Board has eight 7-segment displays. These displays are arranged into two pairs and a group of four, with the intent of displaying numbers of various sizes. As indicated in the schematic in Figure 4.6, the seven segments are connected to pins on the Cyclone II FPGA. Applying a low logic level to a segment causes it to light up, and applying a high logic level turns it off.
DE2 User Manual Signal Name FPGA Pin No.
DE2 User Manual HEX5[1] PIN_P6 Seven Segment Digit 5[1] HEX5[2] PIN_P7 Seven Segment Digit 5[2] HEX5[3] PIN_T9 Seven Segment Digit 5[3] HEX5[4] PIN_R5 Seven Segment Digit 5[4] HEX5[5] PIN_R4 Seven Segment Digit 5[5] HEX5[6] PIN_R3 Seven Segment Digit 5[6] HEX6[0] PIN_R2 Seven Segment Digit 6[0] HEX6[1] PIN_P4 Seven Segment Digit 6[1] HEX6[2] PIN_P3 Seven Segment Digit 6[2] HEX6[3] PIN_M2 Seven Segment Digit 6[3] HEX6[4] PIN_M3 Seven Segment Digit 6[4] HEX6[5] PIN_M5 Seven
DE2 User Manual Figure 4.8. Schematic diagram of the clock circuit. Signal Name FPGA Pin No. Description CLOCK_27 PIN_D13 27 MHz clock input CLOCK_50 PIN_N2 50 MHz clock input EXT_CLOCK PIN_P26 External (SMA) clock input Table 4.5. Pin assignments for the clock inputs. 4.5 Using the LCD Module The LCD module has built-in fonts and can be used to display text by sending appropriate commands to the display controller, which is called HD44780.
DE2 User Manual Figure 4.9. Schematic diagram of the LCD module. Signal Name FPGA Pin No.
DE2 User Manual 4.6 Using the Expansion Header The DE2 Board provides two 40-pin expansion headers. Each header connects directly to 36 pins on the Cyclone II FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC33), and two GND pins. Figure 4.10 shows the related schematics. Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages.
DE2 User Manual GPIO_0[10] PIN_N18 GPIO Connection 0[10] GPIO_0[11] PIN_P18 GPIO Connection 0[11] GPIO_0[12] PIN_G23 GPIO Connection 0[12] GPIO_0[13] PIN_G24 GPIO Connection 0[13] GPIO_0[14] PIN_K22 GPIO Connection 0[14] GPIO_0[15] PIN_G25 GPIO Connection 0[15] GPIO_0[16] PIN_H23 GPIO Connection 0[16] GPIO_0[17] PIN_H24 GPIO Connection 0[17] GPIO_0[18] PIN_J23 GPIO Connection 0[18] GPIO_0[19] PIN_J24 GPIO Connection 0[19] GPIO_0[20] PIN_H25 GPIO Connection 0[20] GPIO_0[21]
DE2 User Manual GPIO_1[11] PIN_P24 GPIO Connection 1[11] GPIO_1[12] PIN_R25 GPIO Connection 1[12] GPIO_1[13] PIN_R24 GPIO Connection 1[13] GPIO_1[14] PIN_R20 GPIO Connection 1[14] GPIO_1[15] PIN_T22 GPIO Connection 1[15] GPIO_1[16] PIN_T23 GPIO Connection 1[16] GPIO_1[17] PIN_T24 GPIO Connection 1[17] GPIO_1[18] PIN_T25 GPIO Connection 1[18] GPIO_1[19] PIN_T18 GPIO Connection 1[19] GPIO_1[20] PIN_T21 GPIO Connection 1[20] GPIO_1[21] PIN_T20 GPIO Connection 1[21] GPIO_1[22]
DE2 User Manual Figure 4.11. VGA circuit schematic. The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on various educational web sites (for example, search for “VGA signal timing”). Figure 4.12 illustrates the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor.
DE2 User Manual Figure 4.12. VGA horizontal timing specification. VGA mode Horizontal Timing Spec Configuration Resolution(HxV) a(us) b(us) c(us) d(us) Pixel clock(Mhz) VGA(60Hz) 640x480 3.8 1.9 25.4 0.6 25 (640/c) VGA(85Hz) 640x480 1.6 2.2 17.8 1.6 36 (640/c) SVGA(60Hz) 800x600 3.2 2.2 20 1 40 (800/c) SVGA(75Hz) 800x600 1.6 3.2 16.2 0.3 49 (800/c) SVGA(85Hz) 800x600 1.1 2.7 14.2 0.6 56 (800/c) XGA(60Hz) 1024x768 2.1 2.5 15.8 0.
DE2 User Manual Signal Name FPGA Pin No.
DE2 User Manual 4.8 Using the 24-bit Audio CODEC The DE2 board provides high-quality 24-bit audio via the Wolfson WM8731 audio CODEC (enCOder/DECoder). This chip supports microphone-in, line-in, and line-out ports, with a sample rate adjustable from 8 kHz to 96 kHz. The WM8731 is controlled by a serial I2C bus interface, which is connected to pins on the Cyclone II FPGA. A schematic diagram of the audio circuitry is shown in Figure 4.15, and the FPGA pin assignments are listed in Table 4.9.
DE2 User Manual 4.9 RS-232 Serial Port The DE2 board uses the MAX232 transceiver chip and a 9-pin D-SUB connector for RS-232 communications. For detailed information on how to use the transceiver refer to the datasheet, which is available on the manufacturer’s web site, and from the Datasheet folder on the DE2 System CD-ROM. Figure 4.16 shows the related schematics, and Table 4.10 lists the Cyclone II FPGA pin assignments. Figure 4.16. MAX232 (RS-232) chip schematic. Signal Name FPGA Pin No.
DE2 User Manual Signal Name FPGA Pin No. Description PS2_CLK PIN_D26 PS/2 Clock PS2_DAT PIN_C24 PS/2 Data Table 4.11. PS/2 pin assignments. 4.11 Fast Ethernet Network Controller The DE2 board provides Ethernet support via the Davicom DM9000A Fast Ethernet controller chip. The DM9000A includes a general processor interface, 16 Kbytes SRAM, a media access control (MAC) unit, and a 10/100M PHY transceiver. Figure 4.
DE2 User Manual ENET_DATA[5] PIN_A17 DM9000A DATA[5] ENET_DATA[6] PIN_B16 DM9000A DATA[6] ENET_DATA[7] PIN_B15 DM9000A DATA[7] ENET_DATA[8] PIN_B20 DM9000A DATA[8] ENET_DATA[9] PIN_A20 DM9000A DATA[9] ENET_DATA[10] PIN_C19 DM9000A DATA[10] ENET_DATA[11] PIN_D19 DM9000A DATA[11] ENET_DATA[12] PIN_B19 DM9000A DATA[12] ENET_DATA[13] PIN_A19 DM9000A DATA[13] ENET_DATA[14] PIN_E18 DM9000A DATA[14] ENET_DATA[15] PIN_D18 DM9000A DATA[15] ENET_CLK PIN_B24 DM9000A Clock 25 MHz EN
DE2 User Manual Figure 4.19. TV Decoder schematic. Signal Name FPGA Pin No.
DE2 User Manual 4.13 Implementing a TV Encoder Although the DE2 board does not include a TV encoder chip, the ADV7123 (10-bit high-speed triple ADCs) can be used to implement a professional-quality TV encoder with the digital processing part implemented in the Cyclone II FPGA. Figure 4.20 shows a block diagram of a TV encoder implemented in this manner. Figure 4.20. A TV Encoder that uses the Cyclone II FPGA and the ADV7123. 4.
DE2 User Manual Figure 4.21. USB (ISP1362) host and device schematic. Signal Name FPGA Pin No.
DE2 User Manual OTG_WR_N PIN_G1 ISP1362 Write OTG_RST_N PIN_G5 ISP1362 Reset OTG_INT0 PIN_B3 ISP1362 Interrupt 0 OTG_INT1 PIN_C3 ISP1362 Interrupt 1 OTG_DACK0_N PIN_C2 ISP1362 DMA Acknowledge 0 OTG_DACK1_N PIN_B2 ISP1362 DMA Acknowledge 1 OTG_DREQ0 PIN_F6 ISP1362 DMA Request 0 OTG_DREQ1 PIN_E5 ISP1362 DMA Request 1 OTG_FSPEED PIN_F3 USB Full Speed, 0 = Enable, Z = Disable OTG_LSPEED PIN_G6 USB Low Speed, 0 = Enable, Z = Disable Table 4.14. USB (ISP1362) pin assignments. 4.
DE2 User Manual 4.16 Using SDRAM/SRAM/Flash The DE2 board provides an 8-Mbyte SDRAM, 512-Kbyte SRAM, and 4-Mbyte (1-Mbyte on some boards) Flash memory. Figures 4.23, 4.24, and 4.25 show the schematics of the memory chips. The pin assignments for each device are listed in Tables 4.16, 4.17, and 4.18. The datasheets for the memory chips are provided in the Datasheet folder on the DE2 System CD-ROM. Figure 4.23. Figure 4.24. SDRAM schematic. SRAM schematic.
DE2 User Manual Figure 4.25. Flash schematic. Signal Name FPGA Pin No.
DE2 User Manual DRAM_DQ[9] PIN_AB2 SDRAM Data[9] DRAM_DQ[10] PIN_AB1 SDRAM Data[10] DRAM_DQ[11] PIN_AA4 SDRAM Data[11] DRAM_DQ[12] PIN_AA3 SDRAM Data[12] DRAM_DQ[13] PIN_AC2 SDRAM Data[13] DRAM_DQ[14] PIN_AC1 SDRAM Data[14] DRAM_DQ[15] PIN_AA5 SDRAM Data[15] DRAM_BA_0 PIN_AE2 SDRAM Bank Address[0] DRAM_BA_1 PIN_AE3 SDRAM Bank Address[1] DRAM_LDQM PIN_AD2 SDRAM Low-byte Data Mask DRAM_UDQM PIN_Y5 SDRAM High-byte Data Mask DRAM_RAS_N PIN_AB4 SDRAM Row Address Strobe DRAM_C
DE2 User Manual SRAM_ADDR[16] PIN_AB8 SRAM Address[16] SRAM_ADDR[17] PIN_AC8 SRAM Address[17] SRAM_DQ[0] PIN_AD8 SRAM Data[0] SRAM_DQ[1] PIN_AE6 SRAM Data[1] SRAM_DQ[2] PIN_AF6 SRAM Data[2] SRAM_DQ[3] PIN_AA9 SRAM Data[3] SRAM_DQ[4] PIN_AA10 SRAM Data[4] SRAM_DQ[5] PIN_AB10 SRAM Data[5] SRAM_DQ[6] PIN_AA11 SRAM Data[6] SRAM_DQ[7] PIN_Y11 SRAM Data[7] SRAM_DQ[8] PIN_AE7 SRAM Data[8] SRAM_DQ[9] PIN_AF7 SRAM Data[9] SRAM_DQ[10] PIN_AE8 SRAM Data[10] SRAM_DQ[11] PIN_AF8
DE2 User Manual FL_ADDR[10] PIN_AE17 FLASH Address[10] FL_ADDR[11] PIN_AF17 FLASH Address[11] FL_ADDR[12] PIN_W16 FLASH Address[12] FL_ADDR[13] PIN_W15 FLASH Address[13] FL_ADDR[14] PIN_AC16 FLASH Address[14] FL_ADDR[15] PIN_AD16 FLASH Address[15] FL_ADDR[16] PIN_AE16 FLASH Address[16] FL_ADDR[17] PIN_AC15 FLASH Address[17] FL_ADDR[18] PIN_AB15 FLASH Address[18] FL_ADDR[19] PIN_AA15 FLASH Address[19] FL_ADDR[20] PIN_Y15 FLASH Address[20] FL_ADDR[21] PIN_Y14 FLASH Address[
DE2 User Manual Chapter 5 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2 board. These circuits provide demonstrations of the major features on the board, such as its audio and video capabilities, and USB and Ethernet connectivity. For each demonstration the Cyclone II FPGA (or EPCS16 serial EEPROM) configuration file is provided, as well as the full source code in Verilog HDL code.
DE2 User Manual • Power on the DE2 board, with the USB cable connected to the USB Blaster port. If necessary (that is, if the default factory configuration of the DE2 board is not currently stored in EPCS16 device), download the bit stream to the board by using either JTAG or AS programming • You should now be able to observe that the 7-segment displays are displaying a sequence of characters, and the red and green LEDs are flashing.
DE2 User Manual Internally, the VGA Controller generates data request and odd/even selected signals to the SDRAM Frame Buffer and filed selection multiplexer(MUX). The YUV422 to YUV444 block converts the selected YCrCb 4:2:2 (YUV 4:2:2) video data to the YCrCb 4:4:4 (YUV 4:4:4) video data format. Finally, the YCrCb_to_RGB block converts the YCrCb data into RGB output. The VGA Controller block generates standard VGA sync signals VGA_HS and VGA_VS to enable the display on a VGA monitor. Figure 5.1.
DE2 User Manual • Connect the audio output of the DVD player to the line-in port of the DE2 board and connect a speaker to the line-out port. If the audio output jacks from the DVD player are of RCA type, then an adaptor will be needed to convert to the mini-stereo plug supported on the DE2 board; this is the same type of plug supported on most computers • Load the bit stream into FPGA. Press KEY0 on the DE2 board to reset the circuit Figure 5.2 illustrates the setup for this demonstration. Figure 5.
DE2 User Manual data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display. Figure 5.3. Block diagram of the USB paintbrush demonstration. Demonstration Setup, File Locations, and Instructions Project directory: DE2_NIOS_HOST_MOUSE_VGA Bit stream used: DE2_NIOS_HOST_MOUSE_VGA.
DE2 User Manual Figure 5.4 illustrates the setup for this demonstration. Figure 5.4. The setup for the USB paintbrush demonstration. 5.4 USB Device Most USB applications and products operate as USB devices, rather than USB hosts. In this demonstration, we show how the DE2 board can operate as a USB device that can be connected to a host computer. As indicated in the block diagram in Figure 5.
DE2 User Manual Figure 5.5. Block diagram of the USB device demonstration. Demonstration Setup, File Locations, and Instructions • • Project directory: DE2_NIOS_DEVICE_LED\HW Bit stream used: DE2_NIOS_DEVICE_LED.sof • • • Nios II Workspace: DE2_NIOS_DEVICE_LED\HW Borland BC++ Software Driver: DE2_NIOS_DEVICE_LED\SW Connect the USB Device connector of the DE2 board to the host computer using a USB cable (type A → B). • • • Load the bit stream into FPGA Run Nios II IDE with HW as the workspace.
DE2 User Manual Figure 5.6. The setup for the USB device demonstration. 5.5 A Karaoke Machine This demonstration uses the microphone-in, line-in, and line-out ports on the DE2 board to create a Karaoke Machine application. The Wolfson WM8731 audio CODEC is configured in the master mode, where the audio CODEC generates AD/DA serial bit clock (BCK) and the left/right channel clock (LRCK) automatically. As indicated in Figure 5.7, the I2C interface is used to configure the Audio CODEC.
DE2 User Manual Demonstration Setup, File Locations, and Instructions • Project directory: DE2_i2sound • • • Bit stream used: DE2_i2sound.sof or DE2_i2sound.
DE2 User Manual On the transmitting side, the Nios II processor sends 64-byte packets every 0.5 seconds to the DM9000A. After receiving the packet, the DM9000A appends a four-byte checksum to the packet and sends it to the Ethernet port. On the receiving side, the DM9000A checks every packet received to see if the destination MAC address in the packet is identical to the MAC address of the DE2 board.
DE2 User Manual Figure 5.10. The setup for the Ethernet demonstration. 5.7 SD Card Music Player Many commercial media/audio players use a large external storage device, such as an SD card or CF card, to store music or video files. Such players may also include high-quality DAC devices so that good audio quality is produced.
DE2 User Manual During operation the Nios II processor will check if the FIFO memory of the Audio DAC Controller becomes full. If the FIFO is not full, the processor will read a 512-byte sector and send the data to the FIFO of the Audio DAC Controller via the Avalon bus. The Audio DAC Controller uses a 48 kHz sample rate to send the data and clock signals to the audio CODEC. The design also mixes the data from microphone-in with line-in for the Karaoke-style effects. Figure 5.11.
DE2 User Manual Figure 5.12. The setup for the SD music player demonstration. 5.8 Music Synthesizer Demonstration This demonstration shows how to implement a Multi-tone Electronic Keyboard using DE2 board with a PS/2 Keyboard and a speaker. PS/2 Keyboard is used as the piano keyboard for input. The Cyclone II FPGA on the DE2 board serves as the Music Synthesizer SOC to generate music and tones. The VGA connected to the DE2 board is used to show which key is pressed during the playing of the music.
DE2 User Manual Figure 5.13. Block diagram of the Music Synthesizer design Demonstration Setup, File Locations, and Instructions • • • • Project directory: DE2_Synthesizer Bit stream used: DE2_Synthesizer.sof or DE2_Synthesizer.pof Connect a PS/2 Keyboard to the DE2 board. Connect the VGA output of the DE2 board to a VGA monitor (both LCD and CRT type of monitors should work) • • • • Connect the Lineout of the DE2 board to a speaker. Load the bit stream into FPGA.
DE2 User Manual Switches and Pushbuttons Signal Name Description KEY[0] Reset Circuit KEY[1] Repeat the Demo Music SW[0] OFF: BRASS, ON: STRING SW[9] OFF: DEMO, ON: PS2 KEYBOARD SW[1] Channel-1 ON / OFF SW[2] Channel-2 ON / OFF Table 5.1. Usage of the switches, pushbuttons (KEYs). • PS/2 Keyboard Signal Name Description Q -#4 A -5 W -#5 S -6 E -#6 D -7 F 1 T #1 G 2 Y #2 H 3 J 4 I #4 K 5 O #5 L 6 P #6 : 7 “ +1 Table 5.2.
DE2 User Manual Figure 5.14. The Setup of the Music Synthesizer Demonstration. Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries.
