User manual

DE2 User Manual
38
Figure 4.11. VGA circuit schematic.
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on
various educational web sites (for example, search for “VGA signal timing”). Figure 4.12 illustrates
the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An
active-low pulse of specific duration (time a in the figure) is applied to the horizontal
synchronization (hsync) input of the monitor, which signifies the end of one row of data and the
start of the next. The data (RGB) inputs on the monitor must be off (driven to 0 V) for a time period
called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c).
During the data display interval the RGB data drives each pixel in turn across the row being
displayed. Finally, there is a time period called the front porch (d) where the RGB signals must
again be off before the next hsync pulse can occur. The timing of the vertical synchronization (vsync)
is the same as shown in Figure 4.12, except that a vsync pulse signifies the end of one frame and the
start of the next, and the data refers to the set of rows in the frame (horizontal timing). Figures 4.13
and 4.14 show, for different resolutions, the durations of time periods a, b, c, and d for both
horizontal and vertical timing.
Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be
found on the manufacturer's web site, and from the Datasheet folder on the DE2 System CD-ROM.
The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table 4.8. An
example of code that drives a VGA display is described in Sections 5.2 and 5.3.