User manual

DE2 User Manual
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4.13 Implementing a TV Encoder
Although the DE2 board does not include a TV encoder chip, the ADV7123 (10-bit high-speed
triple ADCs) can be used to implement a professional-quality TV encoder with the digital
processing part implemented in the Cyclone II FPGA. Figure 4.20 shows a block diagram of a TV
encoder implemented in this manner.
Figure 4.20. A TV Encoder that uses the Cyclone II FPGA and the ADV7123.
4.14 Using USB Host and Device
The DE2 board provides both USB host and device interfaces using the Philips ISP1362 single-chip
USB controller. The host and device controllers are compliant with the Universal Serial Bus
Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s).
Figure 4.21 shows the schematic diagram of the USB circuitry; the pin assignments for the
associated interface are listed in Table 4.14.
Detailed information for using the ISP1362 device is available in its datasheet and programming
guide; both documents can be found on the manufacturer’s web site, and from the Datasheet folder
on the DE2 System CD-ROM. The most challenging part of a USB application is in the design of
the software driver needed. Two complete examples of USB drivers, for both host and device
applications, can be found in Sections 5.3 and 5.4. These demonstrations provide examples of
software drivers for the Nios II processor.