Specifications

June 2012 Altera Corporation
AN-556-2.1 Application Notes
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Using the Design Security Features in
Altera FPGAs
This application note describes how you can use the design security features in
Altera
®
40- and 28-nm FPGAs to protect your designs against unauthorized copying,
reverse engineering, and tampering of your configuration files. This application note
provides the hardware and software requirements for the 40- and 28-nm FPGAs
design security features. This application note also provides steps for implementing a
secure configuration flow.
1 This application note uses the term “40-nm” or “28-nm” FPGAs. Table 1 lists the
supported FPGAs and its applicable devices.
This application note covers the following topics:
■ “Overview of the Design Security Feature” on page 2
■ “Hardware and Software Requirements” on page 5
■ “Steps for Implementing a Secure Configuration Flow” on page 6
■ “Supported Configuration Schemes” on page 25
■ “Security Mode Verification” on page 27
■ “Serial FlashLoader Support with Encryption Enabled” on page 29
■ “JTAG Secure Mode for 28-nm FPGAs” on page 32
■ “US Export Controls” on page 32
In the highly competitive commercial and military environments, design security is
an important consideration for digital designers. As FPGAs start to play a role in
larger and more critical system components, it is ever more important to protect the
designs from unauthorized copying, reverse engineering, and tampering. FPGAs
address these concerns with the ability to decrypt a configuration bitstream using the
256-bit Advanced Encryption Standard (AES) algorithm, an industry standard
encryption algorithm.
Table 1. Supported FPGAs
FPGA Devices
40 nm Arria
®
II and Stratix
®
IV
28 nm Stratix V, Arria V, and Cyclone
®
V