Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Subscribe Send Feedback CV-5V2 2013.11.12 101 Innovation Drive San Jose, CA 95134 www.altera.
TOC-2 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Contents Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices...........1-1 LAB ...............................................................................................................................................................1-1 MLAB ................................................................................................................................................
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration TOC-3 Byte Enable in Embedded Memory Blocks............................................................................................2-13 Byte Enable Controls in Memory Blocks....................................................................................2-13 Data Byte Output...........................................................................................................................2-14 RAM Blocks Operations.........
TOC-4 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Types of Clock Networks................................................................................................................4-3 Clock Sources Per Quadrant..........................................................................................................4-5 Types of Clock Regions...................................................................................................................
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration TOC-5 Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules...........................................................................................................................................5-19 I/O Banks Locations in Cyclone V Devices............................................................................................5-19 I/O Banks Groups in Cyclone V Devices.................................
TOC-6 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Transmitter Blocks.........................................................................................................................5-62 Serializer Bypass for DDR and SDR Operations.......................................................................5-63 Differential Receiver in Cyclone V Devices...........................................................................................
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration TOC-7 Bonding Support............................................................................................................................6-32 Hard Memory Controller Width for Cyclone V E....................................................................6-34 Hard Memory Controller Width for Cyclone V GX................................................................6-35 Hard Memory Controller Width for Cyclone V GT..............
TOC-8 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration JTAG Single-Device Configuration.............................................................................................7-24 JTAG Multi-Device Configuration.............................................................................................7-26 CONFIG_IO JTAG Instruction...................................................................................................7-26 Configuration Data Compression...............
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration TOC-9 JTAG Boundary-Scan Testing in Cyclone V Devices.........................................9-1 BST Operation Control ..............................................................................................................................9-1 IDCODE ...........................................................................................................................................9-1 Supported JTAG Instruction .............
1 Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices 2013.05.06 CV-52001 Subscribe Send Feedback This chapter describes the features of the logic array block (LAB) in the Cyclone® V core fabric. The LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you can configure to implement logic functions, arithmetic functions, and register functions. You can use a quarter of the available LABs in the Cyclone V devices as a memory LAB (MLAB).
1-2 CV-52001 2013.05.06 MLAB Figure 1-1: LAB Structure and Interconnects Overview in Cyclone V Devices This figure shows an overview of the Cyclone V LAB and MLAB structure with the LAB interconnects. C2/C4 C12 Row Interconnects of Variable Speed and Length R14 R3/R6 ALMs Connects to adjacent LABs, memory blocks, digital signal processing (DSP) blocks, or I/O element (IOE) outputs.
CV-52001 2013.05.06 Local and Direct Link Interconnects 1-3 Figure 1-2: LAB and MLAB Structure for Cyclone V Devices You can use an MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM.
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CV-52001 2013.05.06 1-5 ALM Resources Figure 1-4: LAB-Wide Control Signals for Cyclone V Devices This figure shows the clock sources and clock enable signals in a LAB. There are two unique clock signals per LAB. 6 Dedicated Row LAB Clocks 6 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk0 labclk1 labclkena0 or asyncload or labpreset labclr1 syncload labclk2 labclkena1 labclkena2 labclr0 synclr ALM Resources One ALM contains four programmable registers.
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1-8 CV-52001 2013.05.06 Normal Mode Normal Mode Normal mode allows two functions to be implemented in one Cyclone V ALM, or a single function of up to six inputs. Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.
CV-52001 2013.05.06 Shared Arithmetic Mode 1-9 Figure 1-8: ALM in Arithmetic Mode for Cyclone V Devices carry_in datae0 adder0 4-Input LUT dataf0 datac datab dataa reg0 4-Input LUT To General or Local Routing reg1 datad datae1 dataf1 adder1 4-Input LUT 4-Input LUT reg2 To General or Local Routing carry_out reg3 Carry Chain The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode.
1-10 CV-52001 2013.05.06 Document Revision History Figure 1-9: ALM in Shared Arithmetic Mode for Cyclone V Devices shared_arith_in carry_in labclk 4-Input LUT datae0 datac datab dataa reg0 4-Input LUT reg1 4-Input LUT datad datae1 To General or Local Routing reg2 4-Input LUT shared_arith_out reg3 carry_out Shared Arithmetic Chain The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a 3-input adder.
CV-52001 2013.05.06 Document Revision History Date December 2012 June 2012 Version 2012.12.28 2.0 1-11 Changes Reorganized content and updated template. Updated for the Quartus II software v12.0 release: • Restructured chapter. • Updated Figure 1–6. November 2011 1.1 Minor text edits. October 2011 1.0 Initial release.
2 Embedded Memory Blocks in Cyclone V Devices 2013.05.06 CV-52002 Subscribe Send Feedback The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to fit your design requirements. Related Information Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters.
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CV-52002 2013.05.06 Guideline: Implement External Conflict Resolution 2-3 Guideline: Implement External Conflict Resolution In the true dual-port RAM mode, you can perform two write operations to the same memory location. However, the memory blocks do not have internal conflict resolution circuitry. To avoid unknown data being written to the address, implement external conflict resolution logic to the memory block.
2-4 CV-52002 2013.05.06 Mixed-Port Read-During-Write Mode Figure 2-2: Same-Port Read-During-Write: New Data Mode This figure shows sample functional waveforms of same-port read-during-write behavior in the “new data” mode.
CV-52002 2013.05.06 Mixed-Port Read-During-Write Mode Output Mode Memory Type "constrained don't care" MLAB 2-5 Description The RAM outputs “don’t care” or “unknown” value. The Quartus II software analyzes the timing between write and read operations in the MLAB. Figure 2-3: Mixed-Port Read-During-Write: New Data Mode This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “new data” mode.
2-6 CV-52002 2013.05.06 Guideline: Consider Power-Up State and Memory Initialization Figure 2-5: Mixed-Port Read-During-Write: Don’t Care or Constrained Don’t Care Mode This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “don’t care” or “constrained don’t care” mode.
CV-52002 2013.05.06 Guideline: Control Clocking to Reduce Power Consumption 2-7 Related Information • Internal Memory (RAM and ROM) User Guide Provides more information about .mif files. • Quartus II Handbook Provides more information about .mif files. Guideline: Control Clocking to Reduce Power Consumption Reduce AC power consumption in your design by controlling the clocking of each memory block: • Use the read-enable signal to ensure that read operations occur only when necessary.
2-8 CV-52002 2013.05.06 Embedded Memory Configurations Features M10K MLAB Power-up state Output ports are cleared. • Registered output ports—Cleared. • Unregistered output ports—Read memory contents. Asynchronous clears Output registers and output latches Output registers and output latches Write/read operation triggering Rising clock edges Rising clock edges Same-port read-during-write Output ports set to "new data" or "don't care". Output ports set to "don't care".
CV-52002 2013.05.06 2-9 Mixed-Width Port Configurations Mixed-Width Port Configurations The mixed-width port configuration is supported in the simple dual-port RAM and true dual-port RAM memory modes. Note: MLABs do not support mixed-width port configurations. Related Information Internal Memory (RAM and ROM) User Guide Provides more information about dual-port mixed width support.
2-10 CV-52002 2013.05.06 Embedded Memory Modes Port B Port A 8K x 1 4K x 2 2K x 4 2K x 5 1K x 8 1K x 10 512 x 16 512 x 20 — — — Yes — Yes — Yes 512 x 20 Embedded Memory Modes Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the memory block input registers during read or write operations. This is applicable if you use the memory blocks in single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM mode.
CV-52002 2013.05.06 Embedded Memory Clocking Modes Memory Mode ROM M10K Support MLAB Support Yes Yes 2-11 Description You can use the memory blocks as ROM. • Initialize the ROM contents of the memory blocks using a .mif or .hex. • The address lines of the ROM are registered on M10K blocks but can be unregistered on MLABs. • The outputs can be registered or unregistered. • The output registers can be asynchronously cleared.
2-12 CV-52002 2013.05.06 Single Clock Mode Memory Mode Clocking Mode Single-Port Simple DualPort True DualPort ROM FIFO Input/output clock mode Yes Yes Yes Yes — Independent clock mode — — Yes Yes — Note: The clock enable signals are not supported for write address, byte enable, and data input registers on MLAB blocks. Single Clock Mode In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory block.
CV-52002 2013.05.06 Independent Clock Enables in Clocking Modes 2-13 Independent Clock Enables in Clocking Modes Independent clock enables are supported in the following clocking modes: • Read/write clock mode—supported for both the read and write clocks. • Independent clock mode—supported for the registers of both ports. To save power, you can control the shut down of a particular register using the clock enables.
2-14 CV-52002 2013.05.06 Data Byte Output byteena[1:0] Data Bits Written 01 — [9:0] Table 2-13: byteena Controls in x40 Data Width byteena[3:0] Data Bits Written 1111 (default) [39:30] [29:20] [19:10] [9:0] 1000 [39:30] — — — 0100 — [29:20] — — 0010 — — [19:10] — 0001 — — — [9:0] Data Byte Output In M10K blocks, the corresponding masked data byte output appears as a “don’t care” value.
CV-52002 2013.05.06 Memory Blocks Packed Mode Support 2-15 Memory Blocks Packed Mode Support The M10K memory blocks support packed mode. The packed mode feature packs two independent single-port RAM blocks into one memory block. The Quartus II software automatically implements packed mode where appropriate by placing the physical RAM block in true dual-port mode and using the MSB of the address to distinguish between the two logical RAM blocks.
2-16 CV-52002 2013.05.06 Document Revision History Figure 2-9: Address Clock Enable During the Write Cycle Waveform This figure shows the address clock enable waveform during the write cycle.
CV-52002 2013.05.06 Document Revision History Date December 2012 Version 2012.12.28 Changes • Reorganized content and updated template. • Added memory capacity information from the Cyclone V Device Overview for easy reference. • Moved information about supported memory block configurations into its own table. • Added short descriptions of each clocking mode. • Added topic about the packed mode support. • Added topic about the address clock enable support. June 2012 2.0 • Restructured the chapter.
Variable Precision DSP Blocks in Cyclone V Devices 3 2013.05.06 CV-52003 Subscribe Send Feedback This chapter describes how the variable-precision digital signal processing (DSP) blocks in Cyclone V devices are optimized to support higher bit precision in high-performance DSP applications. Related Information Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters.
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CV-52003 2013.05.06 3-3 Resources Resources Table 3-2: Number of Multipliers in Cyclone V Devices The table lists the variable-precision DSP resources by bit precision for each Cyclone V device.
3-4 CV-52003 2013.05.06 Design Considerations Design Considerations You should consider the following elements in your design: • • • • Operational modes Internal coefficient and pre-adder Accumulator Chainout adder Operational Modes The Quartus II software includes megafunctions that you can use to control the operation mode of the multipliers. After entering the parameter settings with the MegaWizard Plug-In Manager, the Quartus II software automatically configures the variable precision DSP block.
CV-52003 2013.05.06 Block Architecture 3-5 Block Architecture The Cyclone V variable precision DSP block consists of the following elements: • • • • • • • • • Input register bank Pre-adder Internal coefficient Multipliers Adder Accumulator and chainout adder Systolic registers Double accumulation register Output register bank If the variable precision DSP block is not configured in systolic FIR mode, both systolic registers are bypassed.
3-6 CV-52003 2013.05.06 Input Register Bank Input Register Bank The input register bank consists of data, dynamic control signals, and two sets of delay registers. All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers. The following variable precision DSP block signals control the input registers within the variable precision DSP block: • CLK[2..0] • ENA[2..
CV-52003 2013.05.06 Input Register Bank 3-7 Figure 3-2: Input Register of a Variable Precision DSP Block in 18 x 19 Mode for Cyclone V Devices The figures show the data registers only. Registers for the control signals are not shown. CLK[2..0] ENA[2..0] scanin[18..0] ACLR[0] dataa_y0[18..0] dataa_z0[17..0] dataa_x0[17..0] Delay registers datab_y1[18..0] datab_z1[17..0] datab_x1[17..0] Delay registers scanout[18..
3-8 CV-52003 2013.05.06 Pre-Adder Figure 3-3: Input Register of a Variable Precision DSP Block in 27 x 27 Mode for Cyclone V Devices The figures show the data registers only. Registers for the control signals are not shown. CLK[2..0] ENA[2..0] scanin[26..0] ACLR[0] dataa_y0[26..0] dataa_z0[25..0] dataa_x0[26..0] scanout[26..0] Pre-Adder Cyclone V Devices Each variable precision DSP block has two 19-bit pre-adders.
CV-52003 2013.05.06 Adder 3-9 There are two multipliers per variable precision DSP block. You can configure these two multipliers in several operational modes: • One 27 x 27 multiplier • Two 18 (signed)/(unsigned) x 19 (signed) multipliers • Three 9 x 9 multipliers Related Information Operational Mode Descriptions on page 3-11 Provides more information about the operational modes of the multipliers.
3-10 CV-52003 2013.05.06 Systolic Registers Function Description NEGATE LOADCONST ACCUMULATE Accumulation Adds the current result to the previous accumulate result. 0 X 1 Decimation This function takes the current result, converts it into two’s complement, and adds it to the previous result. 1 X 1 Systolic Registers There are two systolic registers per variable precision DSP block.
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3-12 CV-52003 2013.05.06 18 x 18 or 18 x 19 Independent Multiplier 18 x 18 or 18 x 19 Independent Multiplier Figure 3-5: Two 18 x 18 or 18 x 19 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices In this figure, the variables are defined as follows: • n = 19 and m = 37 for 18 x 19 mode • n = 18 and m = 36 for 18 x 18 mode Variable-Precision DSP Block Multiplier n data_b1[(n-1)..0] m x [(m-1)..0] 18 n Output Register Bank Input Register Bank data_a1[17..
CV-52003 2013.05.06 20 x 24 Independent Multiplier 3-13 20 x 24 Independent Multiplier Figure 3-7: One 20 x 24 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices In this mode, the result can be up to 52 bits when combined with a chainout adder or accumulator. 24 dataa_a0[23..0] x Output Register Bank 20 dataa_b0[19..0] Input Register Bank Variable-Precision DSP Block Multiplier 44 Result[43..
3-14 CV-52003 2013.05.06 18 x 19 Complex Multiplier 18 x 19 Complex Multiplier Figure 3-10: One 18 x 19 Complex Multiplier with Two Variable Precision DSP Blocks for Cyclone V Devices Variable-Precision DSP Block 1 Multiplier 19 c[18..0] x Adder 19 d[18..0] 18 Multiplier Output Register Bank b[17..0] Input Register Bank 18 + 38 Imaginary Part (ad+bc) x a[17..0] Variable-Precision DSP Block 2 Multiplier 19 x Adder Multiplier - b[17..0] 19 c[18..
CV-52003 2013.05.06 Multiplier Adder Sum Mode 3-15 Multiplier Adder Sum Mode Figure 3-11: One Sum of Two 18 x 19 Multipliers with One Variable Precision DSP Block for Cyclone V Devices Variable-Precision DSP Block SUB_COMPLEX Multiplier 19 dataa_y0[18..0] Chainout adder or accumulator x 18 datab_y1[18..0] +/- Output Register Bank 19 Input Register Bank dataa_x0[17..0] + Multiplier 38 Result[37..0] Adder x 18 datab_x1[17..
3-16 CV-52003 2013.05.06 Systolic FIR Mode Systolic FIR Mode The basic structure of a FIR filter consists of a series of multiplications followed by an addition. Figure 3-13: Basic FIR Filter Equation Depending on the number of taps and the input sizes, the delay through chaining a high number of adders can become quite large. To overcome the delay performance issue, the systolic form is used with additional delay elements placed per tap to increase the performance at the cost of increased latency.
CV-52003 2013.05.06 3-17 27-Bit Systolic FIR Mode Figure 3-15: 18-Bit Systolic FIR Mode for Cyclone V Devices chainin[43..0] 44 dataa_x0[17..0] COEFSELA[2..0] datab_y1[17..0] datab_z1[17..0] +/- 18 Systolic Registers (1) 18 3 x Internal Coefficient +/- + Adder Chainout adder or accumulator Multiplier Pre-Adder 18 18 datab_x1[17..0] 18 COEFSELB[2..0] 3 Output Register Bank dataa_z0[17..0] 18 Input Register Bank dataa_y0[17..
3-18 CV-52003 2013.05.06 Document Revision History Figure 3-16: 27-Bit Systolic FIR Mode for Cyclone V Devices chainin[63..0] 64 Multiplier Pre-Adder +/- 26 dataa_x0[26..0] 27 COEFSELA[2..0] 3 27 Internal Coefficient x +/- + Adder Chainout adder or accumulator Output Register Bank dataa_z0[25..0] 26 Input Register Bank dataa_y0[25..0] 27-bit Systolic FIR 64 chainout[63..0] Document Revision History Date Version Changes May 2013 2013.05.
CV-52003 2013.05.06 Document Revision History Date May 2011 Version 1.0 Changes Initial release.
Clock Networks and PLLs in Cyclone V Devices 4 2013.05.06 CV-52004 Subscribe Send Feedback This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs) in Cyclone V devices. The Quartus II software enables the PLLs and their features without external devices. Related Information Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters.
4-2 CV-52004 2013.05.06 Clock Resources in Cyclone V Devices Table 4-1: Clock Resources in Cyclone V Devices—Preliminary Clock Resource Clock input pins Device Number of Resources Available Source of Clock Resource • Cyclone V E A5, A7, and A9 • Cyclone V GX C4, 24 single-ended or 12 C5, C7, and C9 differential • Cyclone V GT D5, D7, and D9 CLK[0..11][p,n] pins • Cyclone V E A2 and 18 single-ended or 9 A4 differential • Cyclone V GX C3 CLK[0..3][p,n], CLK[6][p,n], CLK[8..
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4-4 CV-52004 2013.05.06 Regional Clock Networks Figure 4-1: GCLK Networks in Cyclone V Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package. CLK[8..11][p,n] GCLK[0..3] Q1 Q4 GCLK[8..11] Q2 Q3 CLK[4..7][p,n] GCLK[12..15] For Cyclone V E A2 and A4 devices, only CLK[6][p,n] pins are available. GCLK network is not available in quadrant 2 for Cyclone V GX C6 device, Cyclone V SE A5 and A6 devices, and Cyclone V ST D5 and D6 devices.
CV-52004 2013.05.06 Periphery Clock Networks 4-5 Periphery Clock Networks Cyclone V devices provide only horizontal PCLKs from the left periphery. Clock outputs from the programmable logic device (PLD)-transceiver interface clocks, horizontal I/O pins, and internal logic can drive the PCLK networks. PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general purpose routing to drive signals into and out of the Cyclone V device.
4-6 CV-52004 2013.05.06 Types of Clock Regions Figure 4-4: Hierarchical Clock Networks in Each Spine Clock Per Quadrant 9 Clock output from the PLL that drives into the SCLKs. GCLK PLL Feedback Clock PCLK RCLK There are up to 12 PCLKs that can drive the SCLKs in each spine clock per quadrant in the largest device. There are up to 22 RCLKs that can drive the SCLKs in each spine clock per quadrant in the largest device.
CV-52004 2013.05.06 Clock Network Sources 4-7 Figure 4-5: Dual-Regional Clock Region for Cyclone V Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package. Clock pins or PLL outputs can drive half of the device to create dual-regional clocking regions for improved interface timing.
4-8 CV-52004 2013.05.06 PLL Clock Outputs Related Information • PLLs and Clocking on page 5-12 Provides more information about HSSI outputs. • LVDS Interface with External PLL Mode on page 5-15 Provides more information about HSSI outputs. PLL Clock Outputs The Cyclone V PLL clock outputs can drive both GCLK and RCLK networks.
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4-10 CV-52004 2013.05.06 Pin Mapping in Cyclone V Devices Pin Mapping in Cyclone V Devices Table 4-6: Mapping Between the Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs Clock Fed by inclk[0] and inclk[1] Any of the four dedicated clock pins on the same side of the Cyclone V device. inclk[2] • PLL counters C0 and C2 from PLLs on the same side of the clock control block (for top, bottom, and right side of the Cyclone V device).
CV-52004 2013.05.06 PCLK Control Block 4-11 Figure 4-7: RCLK Control Block for Cyclone V Devices CLKp Pin PLL Counter Outputs The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input. The CLKn pin can drive the PLL using the RCLK. CLKn Pin 2 Internal Logic Static Clock Select Enable/ Disable When the device is in user mode, you can only set the clock select signals through a configuration file (.sof or .pof); they cannot be controlled dynamically.
4-12 CV-52004 2013.05.06 Clock Power Down Figure 4-9: External PLL Output Clock Control Block for Cyclone V Devices PLL Counter Outputs 9 Static Clock Select When the device is in user mode, you can only set the clock select signals through a configuration file (.sof or .pof); they cannot be controlled dynamically. Enable/ Disable Internal Logic The clock control block feeds to a multiplexer within the FPLL_<#>_CLKOUT pin’s IOE. The FPLL_<#>_CLKOUT pin is a dual-purpose pin.
CV-52004 2013.05.06 Clock Enable Signals 4-13 Figure 4-10: clkena Implementation with Clock Enable and Disable Circuit This figure shows the implementation of the clock enable and disable circuit of the clock control block. The R1 and R2 bypass paths are not available for the PLL external clock outputs. clkena Clock Select Multiplexer Output D Q R1 D Q R2 GCLK/ RCLK/ FPLL_<#>_CLKOUT The select line is statically controlled by a bit setting in the .sof or .pof.
4-14 CV-52004 2013.05.06 Cyclone V PLLs Cyclone V PLLs PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces. The Cyclone V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs. The output counters in Cyclone V devices are dedicated to each fractional PLL that support integer or fractional frequency synthesis.
CV-52004 2013.05.06 PLL Physical Counters in Cyclone V Devices 4-15 PLL Physical Counters in Cyclone V Devices The physical counters for the fractional PLLs are arranged in the following sequences: • Up-to-down • Down-to-up Figure 4-12: PLL Physical Counters Orientation for Cyclone V Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
4-16 CV-52004 2013.05.06 PLL Locations in Cyclone V Devices Figure 4-14: PLL Locations for Cyclone V GX C3 Device This figure represents the top view of the silicon die that corresponds to a reverse view of the device package. CLK[8..11][p,n] Pins CLK[10,11] 2 Logical Clocks 4 Logical Clocks 4 FRACTIONALPLL_X0_Y28 FRACTIONALPLL_X48_Y28 PLL Strip 4 FRACTIONALPLL_X0_Y13 FRACTIONALPLL_X48_Y1 3 4 Logical Clocks Pins CLK[0..
CV-52004 2013.05.06 PLL Locations in Cyclone V Devices 4-17 Figure 4-16: PLL Locations for Cyclone V E A7 Device, Cyclone V GX C7 Device, Cyclone V GT D7 Device, Cyclone V SE A5 and A6 Devices, Cyclone V SX C5 and C6 Devices, and Cyclone V ST D5 and D6 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package. CLK[8..
4-18 CV-52004 2013.05.06 Fractional PLL Architecture Figure 4-17: PLL Locations for Cyclone V E A9 Device, Cyclone V GX C9 Device, and Cyclone V GT D9 Device This figure represents the top view of the silicon die that corresponds to a reverse view of the device package. CLK[8..11][p,n] Pins CLK[10,11] 4 Logical Clocks 2 Logical Clocks 4 FRACTIONALPLL_X0_Y108 FRACTIONALPLL_X121_Y108 2 4 Logical Clocks Pins CLK[4..
CV-52004 2013.05.06 Fractional PLL Usage 4-19 Fractional PLL Usage You can configure the fractional PLL to function either in the integer or in the enhanced fractional mode. One fractional PLL can use up to 9 output counters and all external clock outputs.
4-20 CV-52004 2013.05.06 PLL Control Signals Figure 4-19: Dual-Purpose Clock I/O Pins Associated with PLL for Cyclone V Devices I/O / FPLL_<#>_CLKOUT0/ FPLL_<#>_CLKOUTp / FPLL_<#>_FB EXTCLKOUT[0] C0 fbin C1 C2 You can feed these clock output pins using any one of the C[8..0] or M counters. When not used as external clock outputs, you can use these clock output pins as regular user I/Os.
CV-52004 2013.05.06 locked 4-21 When areset is driven high, the PLL counters reset, clearing the PLL output and placing the PLL out-oflock. The VCO is then set back to its nominal setting. When areset is driven low again, the PLL resynchronizes to its input as it re-locks. You must assert the areset signal every time the PLL loses lock to guarantee the correct phase relationship between the PLL input and output clocks.
4-22 CV-52004 2013.05.06 Source Synchronous Mode Source Synchronous Mode If the data and clock arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. Altera recommends source synchronous mode for source synchronous data transfers.
CV-52004 2013.05.06 Direct Compensation Mode 4-23 Figure 4-21: Example of Phase Relationship Between the Clock and Data in LVDS Compensation Mode Data Pin PLL Reference Clock at the Input Pin Data at the Register Clock at the Register Direct Compensation Mode In direct compensation mode, the PLL does not compensate for any clock networks. This mode provides better jitter performance because the clock feedback into the PFD passes through less circuitry.
4-24 CV-52004 2013.05.06 Zero-Delay Buffer Mode Figure 4-23: Example of Phase Relationship Between the PLL Clocks in Normal Mode Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port Dedicated PLL Clock Outputs The external clock output can lead or lag the PLL internal clock signals. Zero-Delay Buffer Mode In ZDB mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device.
CV-52004 2013.05.06 External Feedback Mode 4-25 Figure 4-24: ZDB Mode in Cyclone V PLLs C0 EXTCLKOUT[0] fbout fbin C1 FPLL_<#>_FB C2 EXTCLKOUT[1] C3 inclk Multiplexer C4 ÷N PFD CP/LF 10 VCO 2 C5 C6 C7 C8 M Figure 4-25: Example of Phase Relationship Between the PLL Clocks in ZDB Mode Phase Aligned PLL Reference Clock at the Input Pin The internal PLL clock output can lead or lag the external PLL clock outputs.
4-26 CV-52004 2013.05.06 External Feedback Mode One of the dual-purpose external clock outputs becomes the fbin input pin in this mode. The external feedback input pin, fbin is phase-aligned with the clock input pin. Aligning these clocks allows you to remove clock delay and skew between devices. When using EFB mode, you must use the same I/O standard on the input clock, feedback input, and clock outputs. This mode is supported only on the corner fractional PLLs.
CV-52004 2013.05.06 Clock Multiplication and Division 4-27 Related Information PLL External Clock I/O Pins on page 4-19 Provides more information about PLL clock outputs. Clock Multiplication and Division Each Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match fin × (M/N).
4-28 CV-52004 2013.05.06 Programmable Duty Cycle Related Information Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide Provides more information about PLL software support in the Quartus II software. Programmable Duty Cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on the PLL post-scale counters. The duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters.
CV-52004 2013.05.06 Automatic Switchover 4-29 Figure 4-28: Automatic Clock Switchover Circuit Block Diagram This figure shows a block diagram of the automatic switchover circuit built into the PLL. clkbad[0] clkbad[1] activeclock Clock Sense Switchover State Machine clksw Clock Switch Control Logic clkswitch inclk0 N Counter inclk1 Multiplexer Out PFD refclk fbclk When the current reference clock is not present, the clock sense block automatically switches to the backup clock for PLL reference.
4-30 CV-52004 2013.05.06 Automatic Switchover with Manual Override period difference is within 20%, the clock sense block detects when a clock stops toggling. However, the PLL may lose lock after the switchover is completed and needs time to relock. Note: Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover.
CV-52004 2013.05.06 Manual Clock Switchover 4-31 Figure 4-30: Clock Switchover Using the clkswitch (Manual) Control This figure shows a clock switchover waveform controlled by the clkswitch signal. In this case, both clock sources are functional and inclk0 is selected as the reference clock; the clkswitch signal goes high, which starts the switchover sequence. On the falling edge of inclk0, the counter’s reference clock, muxout, is gated off to prevent clock glitching.
4-32 CV-52004 2013.05.06 Guidelines Figure 4-31: Manual Clock Switchover Circuitry in Cyclone V PLLs clkswitch Clock Switch Control Logic inclk0 N Counter inclk1 muxout PFD refclk fbclk You can delay the clock switchover action by specifying the switchover delay in the ALTERA_PLL megafunction. When you specify the switchover delay, the clkswitch signal must be held high for at least three inclk cycles plus the number of the delay cycles that has been specified to initiate a clock switchover.
CV-52004 2013.05.06 PLL Reconfiguration and Dynamic Phase Shift 4-33 Figure 4-32: VCO Switchover Operating Frequency Primary Clock Stops Running Switchover Occurs VCO Tracks Secondary Clock ∆Fvco PLL Reconfiguration and Dynamic Phase Shift For more information about PLL reconfiguration and dynamic phase shifting, refer to AN661.
4-34 CV-52004 2013.05.06 Document Revision History Date December 2012 Version Changes 2012.12.28 • Added note to indicate that the figures shown are the top view of the silicon die. • Removed DPA support. • Updated clock resources table. • Updated diagrams for GCLK, RCLK, and PCLK networks. • Updated diagram for clock sources per quadrant. • Updated dual-regional clock region for Cyclone V SoC devices support.
5 I/O Features in Cyclone V Devices 2013.06.21 CV-52005 Subscribe Send Feedback This chapter provides details about the features of the Cyclone V I/O elements (IOEs) and how the IOEs work in compliance with current and emerging I/O standards and requirements.
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5-4 CV-52005 2013.06.21 I/O Vertical Migration for Cyclone V Devices I/O Vertical Migration for Cyclone V Devices Figure 5-1: Vertical Migration Capability Across Cyclone V Device Packages and Densities—Preliminary The arrows indicate the vertical migration paths. The devices included in each vertical migration path are shaded. You can also migrate your design across device densities in the same package option if the devices have the same dedicated pins, configuration pins, and power pins.
CV-52005 2013.06.21 Verifying Pin Migration Compatibility 5-5 Verifying Pin Migration Compatibility You can use the Pin Migration View window in the Quartus II software Pin Planner to assist you in verifying whether your pin assignments migrate to a different device successfully. You can vertically migrate to a device with a different density while using the same device package, or migrate between packages with different densities and ball counts. 1.
5-6 I/O Standard 3.0 V LVTTL/3.0 V LVCMOS 3.0 V PCI (6) (7) CV-52005 2013.06.21 I/O Standards Support for FPGA I/O in Cyclone V Devices (6) Standard Support JESD8-B PCI Rev. 2.2 3.0 V PCI-X (7) PCI-X Rev. 1.0 2.5 V LVCMOS JESD8-5 1.8 V LVCMOS JESD8-7 1.5 V LVCMOS JESD8-11 1.2 V LVCMOS JESD8-12 SSTL-2 Class I JESD8-9B SSTL-2 Class II JESD8-9B SSTL-18 Class I JESD8-15 SSTL-18 Class II JESD8-15 SSTL-15 Class I — SSTL-15 Class II — 1.8 V HSTL Class I JESD8-6 1.
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5-8 CV-52005 2013.06.21 I/O Standards Voltage Levels in Cyclone V Devices I/O Standard Standard Support HPS Column I/O HPS Row I/O SSTL-135 — — Yes SSTL-125 — — Yes HSUL-12 — — Yes I/O Standards Voltage Levels in Cyclone V Devices Table 5-9: Cyclone V I/O Standards Voltage Levels This table lists the typical power supplies for each supported I/O standards in Cyclone V devices.
CV-52005 2013.06.21 I/O Standards Voltage Levels in Cyclone V Devices VCCIO (V) I/O Standard (10) (10) Input 5-9 VCCPD (V) VREF (V) VTT (V) Output (Pre-Driver Voltage) (Input Ref Voltage) (Board Termination Voltage) Differential SSTL-2 Class I VCCPD 2.5 2.5 — 1.25 Differential SSTL-2 Class II VCCPD 2.5 2.5 — 1.25 Differential SSTL-18 Class I VCCPD 1.8 2.5 — 0.9 Differential SSTL-18 Class II VCCPD 1.8 2.5 — 0.9 Differential SSTL-15 Class I VCCPD 1.5 2.5 — 0.
5-10 CV-52005 2013.06.21 MultiVolt I/O Interface in Cyclone V Devices VCCIO (V) I/O Standard (10) Input VCCPD (V) VREF (V) VTT (V) Output (Pre-Driver Voltage) (Input Ref Voltage) (Board Termination Voltage) SSTL-15 VCCPD 1.5 2.5 0.75 SSTL-135 VCCPD 1.35 2.5 0.675 SSTL-125 VCCPD 1.25 2.5 0.625 HSUL-12 VCCPD 1.2 2.5 0.6 Differential SSTL-15 VCCPD 1.5 2.5 — Differential SSTL-135 VCCPD 1.35 2.5 — Differential SSTL-125 VCCPD 1.25 2.
CV-52005 2013.06.21 I/O Design Guidelines for Cyclone V Devices 5-11 Note: If the input signal is 3.0 V or 3.3 V, Altera recommends that you use a clamping diode on the I/O pins. Related Information I/O Standards Voltage Levels in Cyclone V Devices on page 5-8 I/O Design Guidelines for Cyclone V Devices There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.
5-12 PLLs and Clocking CV-52005 2013.06.21 Examples: • An I/O bank can support SSTL-18 inputs and outputs, and 1.8 V inputs and outputs with a 1.8 V VCCIO and a 0.9 V VREF. • An I/O bank can support 1.5 V standards, 1.8 V inputs (but not outputs), and 1.5 V HSTL I/O standards with a 1.5 V VCCIO and 0.75 V VREF. PLLs and Clocking The Cyclone V device family supports fractional PLLs on each side of the device.
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5-14 CV-52005 2013.06.21 Guideline: Using LVDS Differential Channels Both corner PLLs can drive duplex channels in the same I/O bank if the channels that are driven by each PLL are not interleaved. You do not require separation between the groups of channels that are driven by both corner PLLs. Note: The figures in this section show guidelines for using corner PLLs but do not necessarily represent the exact locations of the high-speed LVDS I/O banks.
CV-52005 2013.06.21 LVDS Interface with External PLL Mode 5-15 LVDS Interface with External PLL Mode The MegaWizard Plug-In Manager provides an option for implementing the LVDS interface with the Use External PLL option. With this option enabled you can control the PLL settings, such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings. You must also instantiate the an Altera_PLL megafunction to generate the various clock and load enable signals.
5-16 CV-52005 2013.06.21 Altera_PLL Parameter Values for External PLL Mode Related Information LVDS SERDES Transmitter/Receiver (ALTLVDS_RX/TX) Megafunction User Guide More information about the different clocking requirement for soft SERDES. Altera_PLL Parameter Values for External PLL Mode The following example shows the clocking requirements to generate output clocks for ALTLVDS_TX and ALTLVDS_RX using the Altera_PLL megafunction.
CV-52005 2013.06.21 Connection between Altera_PLL and ALTLVDS 5-17 Connection between Altera_PLL and ALTLVDS Figure 5-4: LVDS Interface with the Altera_PLL Megafunction This figure shows the connections between the Altera_PLL and ALTLVDS megafunction.
5-18 CV-52005 2013.06.21 Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank When planning I/O bank usage for Cyclone V devices, you must ensure the VCCIO voltage is compatible with the VCCPD voltage of the same bank. Some banks may share the same VCCPD power pin. This limits the possible VCCIO voltages that can be used on banks that share VCCPD power pins. Examples: • VCCPD3B is connected to 2.
CV-52005 2013.06.21 Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules 5-19 Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules For Cyclone V LVDS applications, adhere to these guidelines to avoid adverse impact on LVDS performance: • I/O restrictions guideline—to avoid excessive jitter on the LVDS transmitter output pins. • Differential pad placement rule for each device—to avoid crosstalk effects.
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5-26 CV-52005 2013.06.21 Modular I/O Banks for Cyclone V ST Devices Related Information • I/O Banks Locations in Cyclone V Devices on page 5-19 • Guideline: Use the Same VCCPD for All I/O Banks in a Group on page 5-17 Provides guidelines about VCCPD and I/O banks groups. Modular I/O Banks for Cyclone V ST Devices Table 5-22: Modular I/O Banks for Cyclone V ST Devices—Preliminary Note: The HPS row and column I/O counts are the number of HPS-specific I/O pins on the device.
CV-52005 2013.06.21 I/O Buffer and Registers in Cyclone V Devices 5-27 I/O Buffer and Registers in Cyclone V Devices I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to the output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization.
5-28 CV-52005 2013.06.21 Programmable IOE Features in Cyclone V Devices Programmable IOE Features in Cyclone V Devices Table 5-24: Summary of Supported Cyclone V Programmable IOE Features and Settings Feature Setting (Default setting in bold) Condition Slew Rate Control 0 (Slow), 1 (Fast) Disabled if you use the RS OCT feature. Yes I/O Delay Refer to the device datasheet — — Open-Drain Output On, Off — Yes Bus-Hold On, Off Disabled if you use the weak pull-up resistor feature.
CV-52005 2013.06.21 Programmable Current Strength 5-29 Programmable Current Strength You can use the programmable current strength to mitigate the effects of high signal attenuation that is caused by a long transmission line or a legacy backplane. Table 5-25: Programmable Current Strength Settings for Cyclone V Devices The output buffer for each Cyclone V device I/O pin has a programmable current strength control for the I/O standards listed in this table.
5-30 Programmable Output Slew-Rate Control CV-52005 2013.06.21 Programmable Output Slew-Rate Control The programmable output slew-rate control in the output buffer of each regular- and dual-function I/O pin allows you to configure the following: • Fast slew-rate—provides high-speed transitions for high-performance systems. • Slow slew-rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.
CV-52005 2013.06.21 Programmable Pre-Emphasis 5-31 Programmable Pre-Emphasis The VOD setting and the output impedance of the driver set the output current limit of a high-speed transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full VOD level before the next edge, producing pattern-dependent jitter. With pre-emphasis, the output current is boosted momentarily during switching to increase the output slew rate.
5-32 CV-52005 2013.06.21 I/O Pins Features for Cyclone V Devices Figure 5-11: Differential VOD This figure shows the VOD of the differential LVDS output.
CV-52005 2013.06.21 Bus-Hold Circuitry 5-33 Bus-Hold Circuitry Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the configuration. The bus-hold circuitry uses a resistor with a nominal resistance (RBH), approximately 7 kΩ, to weakly pull the signal level to the last-driven state of the pin.
5-34 CV-52005 2013.06.21 RS OCT without Calibration in Cyclone V Devices • RS OCT with Calibration in Cyclone V Devices on page 5-35 • RT OCT with Calibration in Cyclone V Devices on page 5-37 • LVDS Input RD OCT in Cyclone V Devices on page 5-40 • Dynamic OCT in Cyclone V Devices on page 5-39 RS OCT without Calibration in Cyclone V Devices The Cyclone V devices support RS OCT for single-ended and voltage-referenced I/O standards. RS OCT without calibration is supported on output only.
CV-52005 2013.06.21 RS OCT with Calibration in Cyclone V Devices 5-35 Uncalibrated OCT (Output) I/O Standard RS (Ω) Differential SSTL-15 Class II 25 Differential 1.8 V HSTL Class I 50 Differential 1.8 V HSTL Class II 25 Differential 1.5 V HSTL Class I 50 Differential 1.5 V HSTL Class II 25 Differential 1.2 V HSTL Class I 50 Differential 1.
5-36 I/O Standard Calibrated OCT (Output) RS (Ω) (11) RZQ (Ω) 2.5 V LVCMOS 25/50 100 1.8 V LVCMOS 25/50 100 1.5 V LVCMOS 25/50 100 1.2 V LVCMOS 25/50 100 SSTL-2 Class I 50 100 SSTL-2 Class II 25 100 SSTL-18 Class I 50 100 SSTL-18 Class II 25 100 SSTL-15 Class I 50 100 SSTL-15 Class II 25 100 1.8 V HSTL Class I 50 100 1.8 V HSTL Class II 25 100 1.5 V HSTL Class I 50 100 1.5 V HSTL Class II 25 100 1.2 V HSTL Class I 50 100 1.
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5-38 CV-52005 2013.06.21 RT OCT with Calibration in Cyclone V Devices Table 5-31: Selectable I/O Standards for RT OCT With Calibration This table lists the input termination settings for calibrated OCT on different I/O standards. I/O Standard (12) Calibrated OCT (Input) (12) RT (Ω) RZQ (Ω) SSTL-2 Class I 50 100 SSTL-2 Class II 50 100 SSTL-18 Class I 50 100 SSTL-18 Class II 50 100 SSTL-15 Class I 50 100 SSTL-15 Class II 50 100 1.8 V HSTL Class I 50 100 1.
CV-52005 2013.06.21 Dynamic OCT in Cyclone V Devices 5-39 Calibrated OCT (Input) I/O Standard (12) RT (Ω) Differential SSTL-125 RZQ (Ω) 20, 30, 40, 60, 120 240 The RT OCT calibration circuit compares the total impedance of the I/O buffer to the external resistor connected to the RZQ pin. The circuit dynamically enables or disables the transistors until the total impedance of the I/O buffer matches the external resistor. Calibration occurs at the end of the device configuration.
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CV-52005 2013.06.21 OCT Calibration Block in Cyclone V Devices 5-41 OCT Calibration Block in Cyclone V Devices You can calibrate the OCT using any of the available four OCT calibration blocks for each device. Each calibration block contains one RZQ pin. You can use RS and RT OCT in the same I/O bank for different I/O standards if the I/O standards use the same VCCIO supply voltage. You cannot configure the RS OCT and the programmable current strength for the same I/O buffer.
5-42 CV-52005 2013.06.21 OCT Calibration Block Sharing Example I/O banks that do not have calibration blocks share the calibration blocks in the I/O banks that have calibration blocks. All I/O banks support OCT calibration with different VCCIO voltage standards, up to the number of available OCT calibration blocks. You can configure the I/O banks to receive calibration codes from any OCT calibration block with the same VCCIO.
CV-52005 2013.06.21 External I/O Termination for Cyclone V Devices 5-43 • Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User Guide Provides more information about the OCT calibration block. External I/O Termination for Cyclone V Devices Table 5-33: External Termination Schemes for Different I/O Standards I/O Standard External Termination Scheme 3.3 V LVTTL/3.3 V LVCMOS 3.0 V LVVTL/3.0 V LVCMOS 3.0 V PCI 3.0 V PCI-X 2.5 V LVCMOS No external termination required 1.8 V LVCMOS 1.
5-44 CV-52005 2013.06.21 Single-ended I/O Termination I/O Standard External Termination Scheme Differential 1.8 V HSTL Class I Differential 1.8 V HSTL Class II Differential 1.5 V HSTL Class I Differential 1.5 V HSTL Class II Differential HSTL I/O Standard Termination Differential 1.2 V HSTL Class I Differential 1.
CV-52005 2013.06.21 Single-ended I/O Termination 5-45 Figure 5-19: SSTL I/O Standard Termination This figure shows the details of SSTL I/O termination on Cyclone V devices.
5-46 CV-52005 2013.06.21 Differential I/O Termination Figure 5-20: HSTL I/O Standard Termination This figure shows the details of HSTL I/O termination on the Cyclone V devices.
CV-52005 2013.06.21 LVDS, RSDS, SLVS, and Mini-LVDS Termination 5-47 Figure 5-21: Differential SSTL I/O Standard Termination This figure shows the details of Differential SSTL I/O termination on Cyclone V devices.
5-48 CV-52005 2013.06.21 Emulated LVDS, RSDS, and Mini-LVDS Termination Figure 5-23: LVDS and SLVS I/O Standard Termination This figure shows the LVDS and SLVS I/O standards termination. The on-chip differential resistor is available in all I/O banks.
CV-52005 2013.06.21 Emulated LVDS, RSDS, and Mini-LVDS Termination 5-49 Figure 5-24: Emulated LVDS, RSDS, or Mini-LVDS I/O Standard Termination The output buffers, as shown in this figure, are available in all I/O banks. RS and RP values are pending characterization.
5-50 CV-52005 2013.06.21 LVPECL Termination Figure 5-25: Resistor Network Calculation Note: Altera recommends that you perform additional simulations with IBIS or SPICE models to validate that the custom resistor values meet the RSDS or mini-LVDS I/O standard requirements. For information about the data rates supported for external single resistor or three-resistor network, refer to the device datasheet. Related Information • Cyclone V Device Datasheet • National Semiconductor (www.national.
CV-52005 2013.06.21 Dedicated High-Speed Circuitries 5-51 Figure 5-27: LVPECL DC-Coupled Termination LVPECL Output Buffer LVPECL Input Buffer Z0 = 50 Ω 100 Ω Z0 = 50 Ω For information about the VICM specification, refer to the device datasheet. Related Information Cyclone V Device Datasheet Dedicated High-Speed Circuitries The Cyclone V device has dedicated circuitries for differential transmitter and receiver to transmit or receive high-speed differential signals.
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CV-52005 2013.06.21 True LVDS Buffers in Cyclone V Devices 5-55 The following tables list the number of true LVDS buffers supported in Cyclone V devices with these conditions: • The LVDS channel count does not include dedicated clock pins. • Each I/O sub-bank can support up to two independent ALTLVDS interfaces. For example, you can place two ALTLVDS interfaces in bank 8A driven by two different PLLs, provided that the LVDS channels are not interleaved.
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5-62 CV-52005 2013.06.21 Emulated LVDS Buffers in Cyclone V Devices Related Information Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-12 Emulated LVDS Buffers in Cyclone V Devices The Cyclone V device family supports emulated LVDS on all I/O banks: • You can use unutilized true LVDS input buffer as emulated LVDS output buffers (eTX), which use two single-ended output buffers with an external resistor network to support LVDS, mini-LVDS, and RSDS I/O standards.
CV-52005 2013.06.21 Transmitter Clocking 5-63 Transmitter Clocking The fractional PLL generates the parallel clocks (rx_outclock and tx_outclock), the load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock running at serial data rate) that clocks the load and shift registers. You can statically set the serialization factor to x4, x5, x6, x7, x8, x9, or x10 using the Quartus II software. The load enable signal is derived from the serialization factor setting.
5-64 CV-52005 2013.06.21 Differential Receiver in Cyclone V Devices Figure 5-36: Serializer Bypass This figure shows the serializer bypass path. In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is passed directly through the IOE. In SDR and DDR modes, the data width to the IOE is 1 and 2 bits, respectively.
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5-66 CV-52005 2013.06.21 Deserializer Figure 5-39: Receiver Data Realignment Rollover This figure shows a preset value of four bit-times before rollover occurs. The rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has occurred. rx_inclock rx_channel_data_align rx_outclock rx_cda_max Deserializer You can statically set the deserialization factor to x4, x5, x6, x7, x8, x9, or x10 by using the Quartus II software.
CV-52005 2013.06.21 Receiver Clocking for Cyclone V Devices 5-67 You can select the rising edge option with the Quartus II MegaWizard Plug-In Manager. The LVDS_diffioclk clock that is generated by the left and right PLLs clocks the data realignment and deserializer blocks. The following figure shows the LVDS datapath block diagram. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
5-68 CV-52005 2013.06.21 Source-Synchronous Timing Budget Figure 5-42: On-Chip Differential I/O Termination Differential Receiver with On-Chip 100 Ω Termination LVDS Transmitter Z0 = 50 Ω RD Z0 = 50 Ω Table 5-41: Quartus II Software Assignment Editor—On-Chip Differential Termination This table lists the assignment name for on-chip differential termination in the Quartus II software Assignment Editor.
CV-52005 2013.06.21 Differential I/O Bit Position 5-69 Figure 5-43: Bit Orientation in the Quartus II Software This figure shows the data bit orientation of the x10 mode. incloc k/outcloc k MSB 9 data in 10 LVDS Bits 8 7 6 5 4 3 2 LSB 0 1 Differential I/O Bit Position Data synchronization is necessary for successful data transmission at high frequencies.
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CV-52005 2013.06.21 Receiver Skew Margin for LVDS Mode 5-71 Figure 5-45: RSKM Equation Conventions used for the equation: • RSKM—the timing margin between the receiver’s clock input and the data input sampling window. • Time unit interval (TUI)—time period of the serial data. • SW—the period of time that the input data must be stable to ensure that data is successfully sampled by the LVDS receiver. The SW is a device property and varies with device speed grade.
5-72 CV-52005 2013.06.21 Document Revision History For LVDS receivers, the Quartus II software provides an RSKM report showing the SW, TUI, and RSKM values for non-DPA LVDS mode: • You can generate the RSKM report by executing the report_RSKM command in the TimeQuest Timing Analyzer. You can find the RSKM report in the Quartus II compilation report in the TimeQuest Timing Analyzer section.
CV-52005 2013.06.21 Document Revision History Date Version 5-73 Changes • Added the preliminary LVDS channels counts for Cyclone V SE, SX, and ST devices. • Updated the topic about LVDS input RD OCT to remove the requirement for setting the VCCIO to 2.5 V. RD OCT now requires only that the VCCPD is 2.5 V. • Updated the topic about LVPECL termination to improve clarity. May 2013 2013.05.
5-74 CV-52005 2013.06.21 Document Revision History Date Version Changes • Updated the tables listing the number of LVDS channels for the Cyclone V devices: • Removed the F256 package from Cyclone V GX C3 device. • Removed the F324 package from the Cyclone V GX C4 and C5, and Cyclone V GT D5 devices. • Changed the F324 package of the Cyclone V GX C3 device to U324. • Separated the Cyclone V GX C4 and C5 devices to different rows. • Removed the F672 package from Cyclone V E A5.
CV-52005 2013.06.21 Document Revision History Date Version 5-75 Changes • Removed statements about LVDS SERDES being available on top and bottom banks only. • Removed the topic about LVDS direct loopback mode. • Updated the true LVDS buffers count for Cyclone V E, GX, and GT devices. • Added the RSKM equation, description, and high-speed timing diagram. June 2012 2.0 Updated for the Quartus II software v12.0 release: • Restructured chapter.
6 External Memory Interfaces in Cyclone V Devices 2013.05.06 CV-52006 Subscribe Send Feedback The Cyclone V devices provide an efficient architecture that allows you to fit wide external memory interfaces to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are designed to provide high-performance support for existing and emerging external memory standards.
6-2 CV-52006 2013.05.06 External Memory Performance External Memory Performance Table 6-2: External Memory Interface Performance in Cyclone V Devices The maximum and minimum operating frequencies depend on the memory interface standards and the supported delay-locked loop (DLL) frequency listed in the device datasheet. Maximum Frequency (MHz) Voltage (V) Hard Controller Soft Controller 1.5 400 300 300 1.35 400 300 300 DDR2 SDRAM 1.8 400 300 167 LPDDR2 SDRAM 1.
CV-52006 2013.05.06 Guideline: Using DQ/DQS Pins 6-3 Guideline: Using DQ/DQS Pins The following list provides guidelines on using the DQ/DQS pins: • The devices support DQ and DQS signals with DQ bus modes of x8 or x16. Cyclone V devices do not support the x4 bus mode. • You can use the DQSn pins that are not used for clocking as DQ pins. • If you do not use the DQ/DQS pins for memory interfacing, you can use these pins as user I/Os.
6-4 CV-52006 2013.05.06 DQ/DQS Groups in Cyclone V E Table 6-4: DQ/DQS Bus Mode Pins for Cyclone V Devices Data Mask DQSn Support (Optional) Maximum Data Pins per Group x8 Yes Yes 11 x16 Yes Yes 23 Mode DQ/DQS Groups in Cyclone V E Table 6-5: Number of DQ/DQS Groups Per Side in Cyclone V E Devices This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the DQ/DQS groups from the pin table of the specific device.
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6-6 CV-52006 2013.05.06 DQ/DQS Groups in Cyclone V GX Member Code Package 484-pin Ultra FineLine BGA 484-pin FineLine BGA A9 672-pin FineLine BGA 896-pin FineLine BGA Side x8 x16 Top 5 1 Right 4 0 Bottom 6 1 Top 5 1 Right 2 0 Bottom 6 1 Top 7 2 Right 6 0 Bottom 8 2 Top 10 3 Right 10 3 Bottom 10 3 Related Information Cyclone V Device Pin-Out Files Download the relevant pin tables from this web page.
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CV-52006 2013.05.06 6-9 DQ/DQS Groups in Cyclone V GT DQ/DQS Groups in Cyclone V GT Table 6-7: Number of DQ/DQS Groups Per Side in Cyclone V GT Devices This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are available.
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CV-52006 2013.05.06 6-11 DQ/DQS Groups in Cyclone V SX DQ/DQS Groups in Cyclone V SX Table 6-8: Number of DQ/DQS Groups Per Side in Cyclone V SX Devices This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are available.
6-12 CV-52006 2013.05.06 UniPHY IP The following device features are available for external memory interfaces: • • • • • • • DQS phase-shift circuitry PHY Clock (PHYCLK) networks DQS logic block Dynamic on-chip termination (OCT) control IOE registers Delay chains Hard memory controllers UniPHY IP The high-performance memory interface solution includes the self-calibrating UniPHY IP that is optimized to take advantage of the Cyclone V I/O structure and the Quartus II software TimeQuest Timing Analyzer.
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6-18 CV-52006 2013.05.06 DLL Reference Clock Input for Cyclone V Devices I/O banks between two DLLs have the flexibility to create multiple frequencies and multiple-type interfaces. These banks can use settings from either or both adjacent DLLs. For example, DQS1R can get its phase-shift settings from DLL_TR, while DQS2R can get its phase-shift settings from DLL_BR. The reference clock for each DLL may come from the PLL output clocks or clock input pins.
CV-52006 2013.05.06 DLL Phase-Shift 6-19 PLL DLL DLL_BR Top Left Top Right Bottom Left Bottom Right — — — pllout DLL Phase-Shift The DLL can shift the incoming DQS signals by 0° or 90°. The shifted DQS signal is then used as the clock for the DQ IOE input registers, depending on the number of DQS delay chains used. All DQS pins, referenced to the same DLL, can have their input signal phase shifted by a different degree amount but all must be referenced at one particular frequency.
6-20 CV-52006 2013.05.06 PHY Clock (PHYCLK) Networks For the frequency range of each DLL frequency mode, refer to the device datasheet. Related Information Cyclone V Device Datasheet PHY Clock (PHYCLK) Networks The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a highperformance external memory interface. The top and bottom sides of the Cyclone V devices have up to four PHYCLK networks each. There are up to two PHYCLK networks on the left and right side I/O banks.
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CV-52006 2013.05.06 Update Enable Circuitry 6-23 Update Enable Circuitry The update enable circuitry enables the registers to allow enough time for the DQS delay settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic blocks before the next change. Both the DQS delay settings and the phase-offset settings pass through a register before going into the DQS delay chains.
6-24 CV-52006 2013.05.06 Half Data Rate Block that any glitches on the DQS input signal during the end of a read operation and occurring while DQS is in a postamble state do not affect the DQ IOE registers. • For preamble state, the DQS is low, just after a high-impedance state. • For postamble state, the DQS is low, just before it returns to a high-impedance state.
CV-52006 2013.05.06 IOE Registers 6-25 Figure 6-16: Dynamic OCT Control Block for Cyclone V Devices OCT Control Path OCT Control Q D Q D DFF DFF 0 1 OCT Control 1 0 OCT Enable Q D D DFF Q DFF OCT Half-Rate Clock Write Clock The full-rate write clock comes from the PLL. The DQ write clock and DQS write clock have a 90° offset between them Related Information Dynamic OCT in Cyclone V Devices on page 5-39 Provides more information about dynamic OCT control.
6-26 CV-52006 2013.05.06 Output Registers Figure 6-17: IOE Input Registers for Cyclone V Devices Double Data Rate Input Registers DQ D datain [0] Q The input clock can be from the DQS logic block or from a global clock line. DQS/CQ D Q Q DFF Input Reg B To core Read FIFO DFF Input Reg A D dataout[3..
CV-52006 2013.05.06 Delay Chains 6-27 Figure 6-18: IOE Output and Output-Enable Path Registers for Cyclone V Devices The following figure shows the registers available in the Cyclone V output and output-enable paths.
6-28 CV-52006 2013.05.06 I/O and DQS Configuration Blocks Figure 6-19: Delay Chains in an I/O Block OCT Enable Output Enable D5 OCT delay chain D5 output-enable delay chain D5 Delay delay chain DQ or DQS 0 1 D1 Delay delay chain Each DQS logic block contains a delay chain after the dqsbusout output and another delay chain before the dqsenable input.
CV-52006 2013.05.06 Hard Memory Controller 6-29 Figure 6-21: Configuration Block (I/O and DQS) This figure shows the I/O configuration block and the DQS configuration block circuitry. MSB bit2 bit1 bit0 datain update ena rankselectread rankselectwrite dataout clk Related Information ALTDQ_DQS2 Megafunction User Guide Provides details about the I/O and DQS configuration block bit sequence. Hard Memory Controller The Cyclone V devices feature dedicated hard memory controllers.
6-30 CV-52006 2013.05.06 Features of the Hard Memory Controller Feature Description Memory Burst Length • DDR3—Burst length of 8 and burst chop of 4 • DDR2—Burst lengths of 4 and 8 • LPDDR2—Burst lengths of 2, 4, 8, and 16 Command and Data Reordering The controller increases efficiency through the support for out-of-order execution of DRAM commands—with address collision detection-and in-order return of results.
CV-52006 2013.05.06 Multi-Port Front End Feature 6-31 Description Partial Array SelfRefresh You can select the region of memory to refresh during self-refresh through the mode register to save power.
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CV-52006 2013.05.06 Bonding Support 6-33 Figure 6-23: Hard Memory Controllers Bonding Support in Cyclone V E A7, A5, and A9 Devices, Cyclone V GX C4, C5, C7, and C9 Devices, and Cyclone V GT D5, D7, and D9 Devices This figure shows the bonding of two opposite hard memory controllers through the core fabric. The bottom hard memory controller is not supported in the Cyclone V GX C5 device for the 3.3/3.0 V configuration.
6-34 CV-52006 2013.05.06 Hard Memory Controller Width for Cyclone V E Figure 6-24: Hard Memory Controllers in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6 Devices This figure shows hard memory controllers in the SoC FPGAs. There is no bonding support.
CV-52006 2013.05.06 Hard Memory Controller Width for Cyclone V GX 6-35 Member Code Package A2 A4 A5 A7 A9 Top Bottom Top Bottom Top Bottom Top Bottom Top Bottom F484 24 0 24 0 40 24 40 24 24 24 F672 — — — — — — 40 40 40 40 F896 — — — — — — 40 40 40 40 Related Information Guideline: Using DQ/DQS Pins on page 6-3 Important information about usable pin assignments for the hard memory controller in the F484 package of this device.
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CV-52006 2013.05.06 Document Revision History 6-37 Document Revision History Date Version Changes May 2013 2013.05.06 • Moved all links to the Related Information section of respective topics for easy reference. • Added link to the known document issues in the Knowledge Base. • Added the supported minimum operating frequencies for the supported memory interface standards. • Added packages and updated the DQ/DQS groups of Cyclone V E, GX, GT, and SX devices.
6-38 CV-52006 2013.05.06 Document Revision History Date Version Changes • Added the I/O and DQS configuration blocks topic. • Updated the term "Multiport logic" to "multi-port front end" (MPFE). • Added information about the hard memory controller interface widths for the Cyclone V E, GX, GT, SX, and ST variants. June 2012 2.0 Updated for the Quartus II software v12.0 release: • Restructured chapter. • Updated “Design Considerations”, “DQS Postamble Circuitry”, and “IOE Registers”sections.
7 Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices 2013.06.11 CV-52007 Subscribe Send Feedback This chapter describes the configuration schemes, design security, and remote system upgrade that are supported by the Cyclone V devices. Related Information • Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters.
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CV-52007 2013.06.11 Configuration Sequence 7-3 Table 7-2: MSEL Pin Settings for Each Configuration Scheme of Cyclone V Devices Configuration Scheme Compression Feature Design Security Feature VCCPGM (V) Disabled Disabled 1.8/2.5/3.0/3.3 Disabled Enabled 1.8/2.5/3.0/3.3 Enabled Enabled/ Disabled 1.8/2.5/3.0/3.3 Disabled Disabled 1.8/2.5/3.0/3.3 Disabled Enabled 1.8/2.5/3.0/3.3 Enabled Enabled/ Disabled 1.8/2.5/3.0/3.3 PS Enabled/ Disabled Enabled/ Disabled 1.8/2.5/3.0/3.
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CV-52007 2013.06.11 Reset 7-5 The operating voltage for the configuration input pin is independent of the I/O banks power supply, VCCIO, during configuration. Therefore, Cyclone V devices do not require configuration voltage constraints on VCCIO. VCCPD Pin Use the VCCPD pin, a dedicated programming power supply, to power the I/O pre-drivers and JTAG I/O pins (TCK, TMS, TDI, and TDO). The supported configuration voltages are 2.5, 3.0, and 3.3 V. If VCCIO of the bank is set to 2.
7-6 CV-52007 2013.06.11 Initialization Related Information Cyclone V Device Datasheet Provides more information about tSTATUS and tCFG timing parameters. Initialization The initialization clock source is from the internal oscillator, CLKUSR pin, or DCLK pin. By default, the internal oscillator is the clock source for initialization. If you use the internal oscillator, the Cyclone V device will be provided with enough clock cycles for proper initialization.
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7-8 CV-52007 2013.06.11 Configuration Pin Options in the Quartus II Software Configuration Pin Configuration Scheme Input/Output User Mode Powered By PR_READY FPP x16 Output I/O VCCPGM/VCCIO (15) PR_ERROR FPP x16 Output I/O VCCPGM/VCCIO (15) PR_DONE FPP x16 Output I/O VCCPGM/VCCIO (15) Related Information Cyclone V Device Family Pin Connection Guidelines Provides more information about each configuration pin.
CV-52007 2013.06.11 Fast Passive Parallel Configuration 7-9 Fast Passive Parallel Configuration The FPP configuration scheme uses an external host, such as a microprocessor, MAX® II device, or MAX V device. This scheme is the fastest method to configure Cyclone V devices. The FPP configuration scheme supports 8- and 16-bits data width. You can use an external host to control the transfer of configuration data from an external storage such as flash memory to the FPGA.
7-10 CV-52007 2013.06.11 Pin Connections and Guidelines Pin Connections and Guidelines Observe the following pin connections and guidelines for this configuration setup: • Tie the following pins of all devices in the chain together: • • • • • nCONFIG nSTATUS DCLK DATA[] CONF_DONE By tying the CONF_DONE and nSTATUS pins together, the devices initialize and enter user mode at the same time.
CV-52007 2013.06.11 Using One Configuration Data 7-11 When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device in the chain. Configuration automatically begins for the second device in one clock cycle. Using One Configuration Data To configure multiple Cyclone V devices in a chain using one configuration data, connect the devices to an external host as shown in the following figure.
7-12 CV-52007 2013.06.11 Active Serial Single-Device Configuration The maximum DCLK frequency supported by the AS configuration scheme is 100 MHz except for the AS multi-device configuration scheme. You can source DCLK using CLKUSR or the internal oscillator. If you use the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options dialog box, in the Configuration page of the Quartus II software. After power-up, DCLK is driven by a 12.
CV-52007 2013.06.11 Active Serial Multi-Device Configuration 7-13 Figure 7-6: Single Device AS x4 Mode Configuration Connect the pull-up resistors to VCCPGM at 3.0- or 3.3-V power supply. VCCPGM VCCPGM VCCPGM 10 kΩ 10 kΩ 10 kΩ EPCQ Device FPGA Device nSTATUS CONF_DONE nCONFIG nCE GND nCEO DATA2 AS_DATA0/ ASDO MSEL[4..0] AS_DATA1 CLKUSR AS_DATA2 DATA3 AS_DATA3 DATA0 DATA1 DCLK nCS DCLK nCSO N.C. For more information, refer to the MSEL pin settings.
7-14 CV-52007 2013.06.11 Using Multiple Configuration Data Using Multiple Configuration Data To configure multiple Cyclone V devices in a chain using multiple configuration data, connect the devices to an EPCS or EPCQ device, as shown in the following figure. Figure 7-7: Multiple Device AS Configuration When Both Devices in the Chain Receive Different Sets of Configuration Data Connect the pull-up resistors to VCCPGM at a 3.0- or 3.3-V power supply.
CV-52007 2013.06.11 Using EPCS and EPCQ Devices 7-15 Using EPCS and EPCQ Devices EPCS devices support AS x1 mode and EPCQ devices support AS x1 and AS x4 modes. Related Information • Serial Configuration (EPCS) Devices Datasheet • Quad-Serial Configuration (EPCQ) Devices Datasheet Controlling EPCS and EPCQ Devices During configuration, Cyclone V devices enable the EPCS or EPCQ device by driving its nCSO output pin low, which connects to the chip select (nCS) pin of the EPCS or EPCQ device.
7-16 CV-52007 2013.06.11 Programming EPCS Using the JTAG Interface Related Information • AN 370: Using the Serial FlashLoader with the Quartus II Software • AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming Programming EPCS Using the JTAG Interface To program an EPCS device using the JTAG interface, connect the device as shown in the following figure.
CV-52007 2013.06.11 Programming EPCS Using the Active Serial Interface 7-17 Figure 7-9: Connection Setup for Programming the EPCQ Using the JTAG Interface VCCPGM VCCPGM VCCPGM 10 kΩ 10 kΩ 10 kΩ EPCQ Device Connect the pull-up resistors to VCCPGM at a 3.0- or 3.3-V power supply. VCCPD VCCPD FPGA Device nSTATUS CONF_DONE nCONFIG nCE TCK TDO VCCPD TMS TDI Pin 1 GND DATA0 AS_DATA0/ASDO DATA1 AS_DATA1 DATA2 AS_DATA2 Serial AS_DATA3 Flash Loader DCLK MSEL[4..
7-18 CV-52007 2013.06.11 Programming EPCQ Using the Active Serial Interface Figure 7-10: Connection Setup for Programming the EPCS Using the AS Interface Connect the pull-up resistors to VCCPGM at a 3.0- or 3.3-V power supply. VCCPGM VCCPGM VCCPGM 10 kΩ 10 kΩ 10 kΩ FPGA Device CONF_DONE nCEO nSTATUS nCONFIG N.C. EPCS Device nCE 10 kΩ DATA DCLK nCS ASDI AS_DATA1 DCLK nCSO ASDO Pin 1 VCCPGM For more information, refer to the MSEL pin settings. MSEL[4..
CV-52007 2013.06.11 Passive Serial Configuration 7-19 Figure 7-11: Connection Setup for Programming the EPCQ Using the AS Interface Using the AS header, the programmer serially transmits the operation commands and configuration bits to the EPCQ on DATA0. This is equivalent to the programming operation for the EPCS. Connect the pull-up resistors to VCCPGM at a 3.0- or 3.3-V power supply. VCCPGM VCCPGM VCCPGM 10 kΩ 10 kΩ 10 kΩ FPGA Device CONF_DONE nSTATUS nCONFIG nCE EPCQ Device nCEO N.C.
7-20 CV-52007 2013.06.11 Passive Serial Single-Device Configuration Using an External Host the byte sequence 02 1B EE 01 FA, the serial data transmitted to the device must be 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111. You can use the PFL megafunction with a MAX II or MAX V device to read configuration data from the flash memory device and configure the Cyclone V device.
CV-52007 2013.06.11 Passive Serial Multi-Device Configuration 7-21 Figure 7-13: Single Device PS Configuration Using an Altera Download Cable VCCPGM VCCPGM 10 kΩ VCCPGM 10 kΩ VCCPGM 10 kΩ VCCPGM 10 kΩ FPGA Device CONF_DONE nSTATUS 10 kΩ Connect the pull-up resistor to the same supply voltage (VCCIO) as the USB-Blaster, ByteBlaster II, EthernetBlaster, or EthernetBlaster II cable. MSEL[4..0] nCE GND nCEO N.C.
7-22 CV-52007 2013.06.11 Using One Configuration Data Figure 7-14: Multiple Device PS Configuration when Both Devices Receive Different Sets of Configuration Data Connect the resistor to a power supply that provides an acceptable input signal for the FPGA device. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up all the configuration system I/Os with VCCPGM.
CV-52007 2013.06.11 Using PC Host and Download Cable 7-23 The nCE pins of the devices in the chain are connected to GND, allowing configuration for these devices to begin and end at the same time. Using PC Host and Download Cable To configure multiple Cyclone V devices, connect the devices to a download cable, as shown in the following figure.
7-24 CV-52007 2013.06.11 JTAG Single-Device Configuration • JTAG Secure Mode on page 7-34 • AN 425: Using the Command-Line Jam STAPL Solution for Device Programming • Cyclone V Device Datasheet Provides more information about the JTAG configuration timing.
CV-52007 2013.06.11 JTAG Single-Device Configuration 7-25 Figure 7-17: JTAG Configuration of a Single Device Using a Download Cable VCCPD VCCPGM VCCPGM 10 kΩ 10 kΩ GND The resistor value can vary from 1 kΩ to 10 kΩ. Perform signal integrity analysis to select the resistor value for your setup. VCCPD FPGA Device nCE N.C. nCEO TCK TDO Connect the pull-up resistor VCCPD. TMS TDI nSTATUS CONF_DONE nCONFIG MSEL[4..
7-26 CV-52007 2013.06.11 JTAG Multi-Device Configuration JTAG Multi-Device Configuration You can configure multiple devices in a JTAG chain. Pin Connections and Guidelines Observe the following pin connections and guidelines for this configuration setup: • Isolate the CONF_DONE and nSTATUS pins to allow each device to enter user mode independently. • One JTAG-compatible header is connected to several devices in a JTAG chain.
CV-52007 2013.06.11 Configuration Data Compression 7-27 issue all JTAG instructions. Otherwise, you can only issue the BYPASS, IDCODE, and SAMPLE JTAG instructions. You can use the CONFIO_IO JTAG instruction to interrupt configuration and perform board-level testing. After the board-level testing is completed, you must reconfigure your device. Use the following methods to reconfigure your device: • JTAG interface—issue the PULSE_NCONFIG JTAG instruction.
7-28 CV-52007 2013.06.11 Remote System Upgrades Figure 7-20: Compressed and Uncompressed Serial Configuration Data in the Same Configuration File Serial Configuration Data Compressed Configuration Data Decompression Controller Uncompressed Configuration Data FPGA Device 1 nCE EPCS, EPCQ, or External Host FPGA Device 2 nCEO nCE nCEO N.C.
CV-52007 2013.06.11 Configuration Images 7-29 Configuration Images Each Cyclone V device in your system requires one factory image. The factory image is a user-defined configuration image that contains logic to perform the following: • Processes errors based on the status provided by the dedicated remote system upgrade circuitry. • Communicates with the remote host, receives new application images, and stores the images in the local non-volatile memory device.
7-30 CV-52007 2013.06.11 Remote System Upgrade Circuitry Remote System Upgrade Circuitry The remote system upgrade circuitry contains the remote system upgrade registers, watchdog timer, and a state machine that controls these components. Note: If you are using the ALTREMOTE_UPDATE megafunction, the megafunction controls the RU_DOUT, RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN, RU_nCONFIG, and RU_nRSTIMER signals internally to perform all the related remote system upgrade operations.
CV-52007 2013.06.11 Remote System Upgrade Registers 7-31 Related Information Remote System Upgrade (ALTREMOTE_UPDATE) Megafunction User Guide Remote System Upgrade Registers Table 7-6: Remote System Upgrade Registers Register Shift Description Accessible by the logic array and clocked by RU_CLK. • Bits[4..0]—Contents of the status register are shifted into these bits. • Bits[37..0]—Contents of the update and control registers are shifted into these bits.
7-32 CV-52007 2013.06.11 Control Register Control Register Table 7-7: Control Register Bits Bit 0 Name Reset (16) Value 1'b0 AnF Description Application not Factory bit. Indicates the configuration image type currently loaded in the device; 0 for factory image and 1 for application image. When this bit is 1, the access to the control register is limited to read only and the watchdog timer is enabled.
CV-52007 2013.06.11 User Watchdog Timer 7-33 1. After power-up, the remote system upgrade registers are reset to 0 and the factory configuration image is loaded. 2. The user logic sets the AnF bit to 1 and the start address of the application image to be loaded. The user logic also writes the watchdog timer settings. 3.
7-34 CV-52007 2013.06.11 ALTCHIP_ID Megafunction • Security against copying—the security key is securely stored in the Cyclone V device and cannot be read out through any interface. In addition, as configuration file read-back is not supported in Cyclone V devices, your design information cannot be copied.
CV-52007 2013.06.11 Security Key Types 7-35 Security Key Types Cyclone V devices offer two types of keys—volatile and non-volatile. The following table lists the differences between the volatile key and non-volatile keys.
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CV-52007 2013.06.11 Document Revision History 7-37 Document Revision History Date Version Changes June 2013 2013.06.11 Updated the Configuration Error Handling section. May 2013 2013.05.10 Removed support for active serial multi-device configuration using the same configuration data. May 2013 2013.05.06 • Added link to the known document issues in the Knowledge Base. • Added the ALTCHIP_ID megafunction section.
8 SEU Mitigation for Cyclone V Devices 2013.11.12 CV-52008 Subscribe Send Feedback This chapter describes the error detection features in Cyclone V devices. You can use these features to mitigate single event upset (SEU) or soft errors. Related Information Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters.
8-2 CV-52008 2013.11.12 Specifications applications that require the device to operate error-free may require that your designs account for these errors. You can enable the error detection circuitry to detect soft errors. Each data frame stored in the CRAM contains a 32-bit precomputed CRC value. When this feature is enabled, the error detection circuitry continuously computes a 32-bit CRC value for each frame in the CRAM and compares the CRC value against the precomputed value.
CV-52008 2013.11.12 Error Detection Frequency Variant Member Code Timing Interval (µs) D5 1.79 D7 2.33 D9 3.23 A2 1.77 A4 1.77 A5 2.31 A6 2.31 C4 1.77 C5 2.31 C6 2.31 D5 2.31 D6 2.31 Cyclone V GT Cyclone V SE Cyclone V SX Cyclone V ST 8-3 Error Detection Frequency You can control the speed of the error detection process by setting the division factor of the clock frequency in the Quartus II software. The divisor is 2n, where n can be any value listed in the following table.
8-4 CV-52008 2013.11.12 Using Error Detection Features in User Mode Table 8-3: CRC Calculation Time in Cyclone V Devices The following table lists the minimum and maximum time taken to calculate the CRC value: • The minimum time is derived using the maximum clock frequency with a divisor of 0. • The maximum time is derived using the minimum clock frequency with a divisor of 8.
CV-52008 2013.11.12 CRC_ERROR Pin 8-5 3. In the Category list, click Error Detection CRC. 4. Turn on Enable Error Detection CRC_ERROR pin. 5. To set the CRC_ERROR pin as output open drain, turn on Enable open drain on CRC_ERROR pin. Turning off this option sets the CRC_ERROR pin as output. 6. In the Divide error check frequency by list, select a valid divisor. 7. Click OK.
8-6 CV-52008 2013.11.12 Error Detection Registers Table 8-5: Error Detection Registers Name Width (Bits) Description Syndrome register 32 Contains the 32-bit CRC signature calculated for the current frame. If the CRC value is 0, the CRC_ERROR pin is driven low to indicate no error. Otherwise, the pin is pulled high. Error message register (EMR) 67 Contains error details for single-bit and double-adjacent errors.
CV-52008 2013.11.12 Error Detection Process 8-7 Table 8-6: Error Type in EMR The following table lists the possible error types reported in the error type field in the EMR. Error Type Bit 3 Bit 2 Bit 1 Description Bit 0 0 0 0 0 No CRC error. 0 0 0 1 Location of a single-bit error is identified. 0 0 1 0 Location of a double-adjacent error is identified. 1 1 1 1 Error types other than single-bit and double-adjacent errors.
8-8 CV-52008 2013.11.12 Testing the Error Detection Block comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock cycles. To ensure information integrity, complete the read operation within one frame of the CRC verification. The following diagram shows the timing of these events.
CV-52008 2013.11.12 Document Revision History 8-9 Table 8-8: EDERROR_INJECT instruction JTAG Instruction Instruction Code 00 0001 0101 EDERROR_INJECT Description Use this instruction to inject errors into the configuration data. This instruction controls the JTAG fault injection register, which contains the error you want to inject into the bitstream. You can only inject errors into the first frame of the configuration data. However, you can monitor the error information at any time.
JTAG Boundary-Scan Testing in Cyclone V Devices 9 2013.05.06 CV-52009 Subscribe Send Feedback This chapter describes the boundary-scan test (BST) features in Cyclone V devices. Related Information • JTAG Configuration on page 7-23 Provides more information about JTAG configuration. • Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters. BST Operation Control Cyclone V devices support IEEE Std. 1149.1 BST.
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9-4 CV-52009 2013.05.06 Supported JTAG Instruction JTAG Instruction Instruction Code Description BYPASS 11 1111 1111 Places the 1-bit bypass register between the TDI and TDO pins. During normal device operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices. USERCODE 00 0000 0111 • Examines the user electronic signature (UES) within the devices along a JTAG chain.
CV-52009 2013.05.06 Supported JTAG Instruction JTAG Instruction Instruction Code 9-5 Description CLAMP 00 0000 1010 • Places the 1-bit bypass register between the TDI and TDO pins. During normal operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices while holding the I/O pins to a state defined by the data in the boundary-scan register.
9-6 CV-52009 2013.05.06 JTAG Secure Mode Note: If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODE might not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high. Related Information • JTAG Secure Mode on page 7-34 Provides more information about PULSE_NCONFIG, CONFIG_IO, LOCK, and UNLOCK JTAG instructions.
CV-52009 2013.05.06 Performing BST 9-7 Table 9-3: Supported TDO and TDI Voltage Combinations The TDO output buffer for VCCPD of 3.3 V or 3.0 V meets VOH (MIN) of 2.4 V, and the TDO output buffer for VCCPD of 2.5 V meets VOH (MIN) of 2.0 V. Device Cyclone V Non-Cyclone V(20) TDI Input Buffer Power (V) Cyclone V TDO VCCPD VCCPD = 3.3 V VCCPD = 3.0 V VCCPD = 2.5 V VCCPD = 3.3 Yes Yes Yes VCCPD = 3.0 Yes Yes Yes VCCPD = 2.5 Yes Yes Yes VCC = 3.3 Yes Yes Yes VCC = 2.
9-8 CV-52009 2013.05.06 Enabling and Disabling IEEE Std. 1149.1 BST Circuitry Enabling and Disabling IEEE Std. 1149.1 BST Circuitry The IEEE Std. 1149.1 BST circuitry is enabled after the Cyclone V device powers up. However for Cyclone V SoC FPGAs, you must power up both HPS and FPGA to perform BST. To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.
CV-52009 2013.05.06 IEEE Std. 1149.1 Boundary-Scan Register 9-9 IEEE Std. 1149.1 Boundary-Scan Register The boundary-scan register is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. The boundary-scan register consists of 3-bit peripheral elements that are associated with Cyclone V I/O pins. You can use the boundary-scan register to test external pin connections or to capture internal data.
9-10 CV-52009 2013.05.06 Boundary-Scan Cells of a Cyclone V Device I/O Pin Figure 9-2: User I/O BSC with IEEE Std. 1149.
CV-52009 2013.05.06 Document Revision History Captures Output Capture Register Pin Type Dedicated bidirectional (open drain) 9-11 Drives OE Capture Register Input Capture Register Output Update Register OE Update Register Input Update Register Comments 0 OEJ PIN_IN N.C. N.C. N.C. PIN_IN drives to the configuration control Dedicated bidirectional(24) OUTJ OEJ PIN_IN N.C. N.C. N.C.
Power Management in Cyclone V Devices 10 2013.06.28 CV-52010 Subscribe Send Feedback This chapter describes the hot-socketing feature, power-on reset (POR) requirements, and their implementation in Cyclone V devices. Related Information • Cyclone V Device Handbook: Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters. • PowerPlay Power Analysis Provides more information about the Quartus®II PowerPlay Power Analyzer tool.
10-2 CV-52010 2013.06.28 Hot-Socketing Feature The equation shows that power is design-dependent and is determined by the operating frequency of your design. Cyclone V devices minimize static and dynamic power using advanced process optimizations. This technology allows Cyclone V designs to meet specific performance requirements with the lowest possible power. Hot-Socketing Feature Cyclone V devices support hot socketing—also known as hot plug-in or hot swap.
CV-52010 2013.06.28 Power-Up Sequence 10-3 Hot-socketing circuitry prevents excess I/O leakage during power up. When the voltage ramps up very slowly, I/O leakage is still relatively low, even after the release of the POR signal and configuration is complete. Note: The output buffer cannot flip from the state set by the hot-socketing circuitry at very low voltage. To allow the CONF_DONE and nSTATUS pins to operate during configuration, the hot-socketing feature is not applied to these configuration pins.
10-4 CV-52010 2013.06.28 Power-Up Sequence Figure 10-3: Power-Up Sequence Recommendation for Cyclone V Devices Power up VCCBAT at any time. Ramp up the power rails in each group to a minimum of 80% of their full rail before the next group starts. Power up VCCE_GXB and VCCL_GXB together with VCC. 1.1V 2.
CV-52010 2013.06.28 Power-On Reset Circuitry 10-5 For details about the minimum current requirements, refer to the PowerPlay Early Power Estimator (EPE), and compare to the information listed in Table 10-1. If the current transient exceeds the minimum current requirements in the PowerPlay EPE, you need to take the information into consideration for your power regulator design.
10-6 CV-52010 2013.06.28 Power Supplies Monitored and Not Monitored by the POR Circuitry The POR circuitry checks the functionality of the I/O level shifters powered by the VCCPD and VCCPGM power supplies during power-up mode. The main POR circuitry waits for all the individual POR circuitries to release the POR signal before allowing the control block to start programming the device.
CV-52010 2013.06.28 Document Revision History 10-7 Document Revision History Date Version Changes June 2013 2013.06.28 • Added power-up sequences for Cyclone V SX, SE and ST devices. • Added the current transient that occurs on HPS power rails during power-up May 2013 2013.05.06 • Added link to the known document issues in the Knowledge Base. • Moved all links to the Related Information section of respective topics for easy reference.
