Specifications

Figure 3-16: 27-Bit Systolic FIR Mode for Cyclone V Devices
Input Register Bank
dataa_y0[25..0]
dataa_z0[25..0]
dataa_x0[26..0]
COEFSELA[2..0]
Pre-Adder
+/-
Internal
Coefficient
Multiplier
Adder
+/-
Chainout adder or
accumulator
+
chainin[63..0]
chainout[63..0]
27-bit Systolic FIR
27
x
Output Register Bank
26
3
27
26
64
64
Document Revision History
ChangesVersionDate
• Added link to the known document issues in the Knowledge Base.
• Moved all links to the Related Information section of respective topics
for easy reference.
• Updated the variable DSP blocks and multipliers counts for the
Cyclone V SX device variants.
2013.05.06May 2013
• Added resources for Cyclone V devices.
• Updated design considerations for Cyclone V devices in operational
modes.
• Updated Figure 3-10, changed 37 to 38.
• Updated Figure 3-11, changed 37 to 38 and changed Result[36..0] to
Result [37..0].
2012.12.28December 2012
Updated for the Quartus II software v12.0 release:
• Restructured chapter.
• Added “Design Considerations”, “Adder”, and “Double Accumulation
Register” sections.
• Updated Figure 3–1 and Figure 3–13.
• Added Table 3–3.
• Updated “Systolic Registers” and “Systolic FIR Mode” sections.
• Added Equation 3–2.
• Added Figure 3–12.
2.0June 2012
Variable Precision DSP Blocks in Cyclone V Devices
Altera Corporation
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Document Revision History
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2013.05.06