Specifications
Figure 4-19: Dual-Purpose Clock I/O Pins Associated with PLL for Cyclone V Devices
C0
C1
C2
C3
C4
C5
C6
C7
C8
M
I/O / FPLL_<#>_CLKOUT0/ FPLL_<#>_CLKOUTp /
FPLL_<#>_FB
I/O / FPLL_<#>_CLKOUT1 /FPLL_<#>_ CLKOUTn
I/O /FPLL_<#>_FBp
fbin
EXTCLKOUT[0]
EXTCLKOUT[1]
EXTCLKOUT[1..0]
VCO
Fractional PLL
I/O / FPLL_<#>_FBn
210
You can feed these clock output pins using
any one of the C[8..0] or M counters. When
not used as external clock outputs, you can
use these clock output pins as regular user
I/Os.
The FPLL_<#>_CLKOUT0 and
FPLL_<#>_CLKOUT1 pins are single-ended
clock output pins.
The FPLL_<#>_CLKOUTp and
FPLL_<#>_CLKOUTn pins are differential
output pins while the FPLL_<#>_FBp and
FPLL_<#>_FBn pins are differential
feedback input pins to support differential
EFB.
The FPLL_<#>_FB pin is a
single-ended feedback input pin for
single-ended EFB mode.
Each pin of a single-ended output pair can be either in-phase or 180° out-of-phase. To implement the 180°
out-of-phase pin in a pin pair, the Quartus II software places a NOT gate in the design into the IOE.
The clock output pin pairs support the following I/O standards:
• Same I/O standard for the pin pairs
• LVDS
• Differential high-speed transceiver logic (HSTL)
• Differential SSTL
Cyclone V PLLs can drive out to any regular I/O pin through the GCLK or RCLK network. You can also
use the external clock output pins as user I/O pins if you do not require external PLL clocking.
Related Information
• I/O Features in Cyclone V Devices
Provides more information about I/O standards supported by the PLL clock input and output pins.
• Zero-Delay Buffer Mode on page 4-24
• External Feedback Mode on page 4-25
PLL Control Signals
You can use the areset signal to control PLL operation and resynchronization, and use the locked signal
to observe the status of the PLL.
areset
The areset signal is the reset or resynchronization input for each PLL. The device input pins or internal
logic can drive these input signals.
Clock Networks and PLLs in Cyclone V Devices
Altera Corporation
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PLL Control Signals
4-20
2013.05.06