Specifications

Verifying Pin Migration Compatibility
You can use the Pin Migration View window in the Quartus II software Pin Planner to assist you in verifying
whether your pin assignments migrate to a different device successfully. You can vertically migrate to a
device with a different density while using the same device package, or migrate between packages with
different densities and ball counts.
1. Open Assignments > Pin Planner and create pin assignments.
2. If necessary, perform one of the following options to populate the Pin Planner with the node names in
the design:
• Analysis & Elaboration
• Analysis & Synthesis
• Fully compile the design
3. Then, on the menu, click View > Pin Migration View.
4. To select or change migration devices:
a. Click Device to open the Device dialog box.
b. Under Migration compatibility click Migration Devices.
5. To show more information about the pins:
a. Right-click anywhere in the Pin Migration View window and select Show Columns.
b. Then, click the pin feature you want to display.
6. If you want to view only the pins, in at least one migration device, that have a different feature than the
corresponding pin in the migration result, turn on Show migration differences.
7. Click Pin Finder to open the Pin Finder dialog box and find and highlight pins with specific functionality.
If you want to view only the pins found and highlighted by the most recent query in the Pin Finder dialog
box, turn on Show only highlighted pins.
8. To export the pin migration information to a Comma-Separated Value File (.csv), click Export.
Related Information
• I/O Vertical Migration for Cyclone V Devices on page 5-4
• I/O Management chapter, Quartus II Handbook
Provides more information about vertical I/O migrations.
I/O Standards Support in Cyclone V Devices
This section lists the I/O standards supported in the FPGA I/Os and HPS I/Os of Cyclone V devices, the
typical power supply values for each I/O standard, and the MultiVolt I/O interface feature.
I/O Standards Support for FPGA I/O in Cyclone V Devices
Table 5-7: Supported I/O Standards in FPGA I/O for Cyclone V Devices
Standard SupportI/O Standard
JESD8-B3.3 V LVTTL/3.3 V LVCMOS
Altera Corporation
I/O Features in Cyclone V Devices
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Verifying Pin Migration Compatibility
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2013.06.21