Specifications

5–20 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/e Core
f For information regarding data cache bypass methods, refer to the
Processor Architecture chapter of the Nios II Processor Reference Handbook.
Instruction Execution Stages
This section provides an overview of the pipeline behavior as a means of
estimating assembly execution time. Most application programmers
never need to analyze the performance of individual instructions.
Instruction Performance
The Nios II/e core dispatches a single instruction at a time, and the
processor waits for an instruction to complete before fetching and
dispatching the next instruction. Because each instruction completes
before the next instruction is dispatched, branch prediction is not
necessary. This greatly simplifies the consideration of processor stalls.
Maximum performance is one instruction per six clock cycles. To achieve
six cycles, the Avalon-MM instruction master port must fetch an
instruction in one clock cycle. A stall on the Avalon-MM instruction
master port directly extends the execution time of the instruction.
Execution performance for all instructions is shown in Table 5–11.
Table 5–11. Instruction Execution Performance for Nios II/e Core
Instruction Cycles
Normal ALU instructions (e.g., add,
cmplt)
6
branch, jmp, jmpi, ret, call,
callr
6
trap, break, eret, bret,
flushp, wrctl, rdctl,
unimplemented
6
load word
6 + Duration of Avalon-MM read transfer
load halfword
9 + Duration of Avalon-MM read transfer
load byte
10 + Duration of Avalon-MM read transfer
store
6 + Duration of Avalon-MM write transfer
Shift, rotate
7 to 38
All other instructions 6
Combinatorial custom instructions 6
Multi-cycle custom instructions ≥6