Specifications

Altera Corporation 8–61
October 2007 Nios II Processor Reference Handbook
ldb / ldbio
ldb / ldbio
load byte from memory or I/O peripheral
Operation:
rB
←
σ (Mem8[rA + σ (IMM16)])
Assembler Syntax:
ldb rB, byte_offset(rA)
ldbio rB, byte_offset(rA)
Example:
ldb r6, 100(r5)
Description: Computes the effective byte address specified by the sum of rA and the instruction's
signed 16-bit immediate value. Loads register rB with the desired memory byte, sign
extending the 8-bit value to 32 bits. In Nios II processor cores with a data cache, this
instruction may retrieve the desired data from the cache instead of from memory.
Usage:
Use the
ldbio instruction for peripheral I/O. In processors with a data cache, ldbio
bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. In
processors without a data cache,
ldbio acts like ldb.
For more information on data cache, see the Cache and Tightly-Coupled Memory
chapter of the Nios II Software Developer's Handbook.
Instruction Type: I
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
313029282726252423222120191817161514131211109876543210
A B IMM16 0x07
Instruction format for
ldb
313029282726252423222120191817161514131211109876543210
A B IMM16 0x27
Instruction format for
ldbio