Specifications

Altera Corporation 8–93
October 2007 Nios II Processor Reference Handbook
stb / stbio
stb / stbio
store byte to memory or I/O peripheral
Operation:
Mem8[rA + σ (IMM16)]
←
rB
7..0
Assembler Syntax:
stb rB, byte_offset(rA)
stbio rB, byte_offset(rA)
Example:
stb r6, 100(r5)
Description: Computes the effective byte address specified by the sum of rA and the instruction's
signed 16-bit immediate value. Stores the low byte of rB to the memory byte specified
by the effective address.
Usage: In processors with a data cache, this instruction may not generate an Avalon-MM bus
cycle to non-cache data memory immediately. Use the
stbio instruction for
peripheral I/O. In processors with a data cache,
stbio bypasses the cache and is
guaranteed to generate an Avalon-MM data transfer. In processors without a data
cache,
stbio acts like stb.
Instruction Type: I
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
313029282726252423222120191817161514131211109876543210
A B IMM16 0x05
Instruction format for
stb
313029282726252423222120191817161514131211109876543210
A B IMM16 0x25
Instruction format for
stbio