Specifications

Altera Corporation 3–3
October 2007 Nios II Processor Reference Handbook
Programming Model
1 When writing to control registers, all undefined bits must be
written as zero.
For details on the relationship between the control registers and exception
processing, see Figure 3–1 on page 3–9.
status
The value in the status register controls the state of the Nios II
processor. All status bits are cleared at processor reset. Some bits are
exclusively used by and available only to certain features of the processor.
Table 3–3 shows descriptions for the defined bits.
estatus
The estatus register holds a saved copy of the status register during
non-break exception processing. One bit is defined: EPIE. This is the
saved value of PIE, as defined in Table 3–3.
The exception handler can examine estatus to determine the pre-
exception status of the processor. When returning from an exception, the
eret instruction causes the processor to copy estatus back to status,
restoring the pre-exception value of status. See “Exception Processing”
on page 3–5 for more information.
Table 3–2. Control Register Names and Bits
Register Name 31…1 0
0
status
Reserved
PIE
1
estatus
Reserved
EPIE
2
bstatus
Reserved
BPIE
3
ienable
Interrupt-enable bits
4
ipending
Pending-interrupt bits
5
cpuid
Unique processor identifier
6-31 Reserved Reserved
Table 3–3. Status Register Bit Descriptions
Bit Description Access Reset Available
PIE PIE is the processor interrupt-enable bit. When PIE is zero,
interrupts are ignored. When
PIE is one, interrupts can be taken,
depending on the value of the ienable register.
Read/Write 0 Always