Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History
Altera Corporation 3–21
October 2007 Nios II Processor Reference Handbook
Programming Model
Custom Instructions
The custom instruction provides low-level access to custom instruction
logic. The inclusion of custom instructions is specified at system
generation time, and the function implemented by custom instruction
logic is design dependent.
f For further details, see the “Custom Instructions” section of the Processor
Architecture chapter of the Nios II Processor Reference Handbook and the
Nios II Custom Instruction User Guide.
Machine-generated C functions and assembly macros provide access to
custom instructions, and hide implementation details from the user.
Therefore, most software developers never use the custom assembly
instruction directly.
No-Operation Instruction
The Nios II assembler provides a no-operation instruction, nop.
Potential Unimplemented Instructions
Some Nios II processor cores do not support all instructions in hardware.
In this case, the processor generates an exception after issuing an
unimplemented instruction. Only the following instructions can generate
an unimplemented instruction exception:
■ mul
■ muli
■ mulxss
■ mulxsu
■ mulxuu
■ div
■ divu
All other instructions are guaranteed not to generate an unimplemented
instruction exception.
An exception routine must exercise caution if it uses these instructions,
because they could generate another exception before the previous
exception is properly handled. See “Unimplemented Instruction” on
page 3–10 for details regarding unimplemented instruction processing.
Referenced
Documents
This chapter references the following documents:
■ Nios II Software Developer’s Handbook