Specifications

5–8 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/f Core
The Nios II/f core implements all the data cache bypass methods.
f For information regarding the data cache bypass methods, refer to the
Processor Architecture chapter of the Nios II Processor Reference Handbook
Mixing cached and noncached accesses to the same cache line can result
in invalid data reads. For example, the following sequence of events
causes cache incoherency.
1. The Nios II core writes data to cache, creating a dirty data cache line.
2. The Nios II core reads data from the same address, but bypasses the
cache.
Software should not mix both cached and uncached accesses to the same
cache line. If it is necessary to mix cached and uncached data accesses,
flush the corresponding line of the data cache after completing the cached
accesses and before performing the uncached accesses.
Bursting
When the data cache is enabled, you can enable bursting on the data
master port. Consult the documentation for memory devices connected
to the data master port to determine whether bursting will improve
performance.
Tightly-Coupled Memory
The Nios II/f core provides optional tightly-coupled memory interfaces
for both instructions and data. A Nios II/f core can use up to four each of
instruction and data tightly-coupled memories. When a tightly-coupled
memory interface is enabled, the Nios II core includes an additional
memory interface master port. Each tightly-coupled memory interface
must connect directly to exactly one memory slave port.
When tightly-coupled memory is present, the Nios II core decodes
addresses internally to determine if requested instructions or data reside
in tightly-coupled memory. If the address resides in tightly-coupled
memory, the Nios II core fetches the instruction or data through the
tightly-coupled memory interface. Software accesses tightly-coupled
memory with the usual load and store instructions, such as ldw or
ldwio.