User guide

1–2 Chapter 1: Introduction
PCS
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Figure 1–1 illustrates the top level modules that comprise the transceiver PHY IP
cores. In addition, Figure 1–1 shows the Altera Transceiver Reconfiguration Controller
IP core that is instantiated separately in Stratix V devices.
The following sections provide a brief introduction to each of the modules illustrated
in Figure 1–1.
PCS
The PCS implements part of the physical layer specification for networking protocols.
Depending upon the protocol that you choose, the PCS may include many different
functions. Some of the most commonly included functions are: 8B/10B, 64B/66B, or
64B/67B encoding and decoding, rate matching and clock compensation, scrambling
and de-scrambling, word alignment, phase compensation, error monitoring, and
gearbox.
Figure 1–1. Altera Modular PHY Design
To MAC
To
Embedded
Controller
To HSSI Pins
Stratix V Device
Transceiver PHY
PMA PCS
Customized functionality
as required for:
10GBase-R
XAUI
Interlaken
PCI Express PIPE
Custom
Low Latency
Avalon-ST
Tx and Rx
Avalon-MM
Control & Status
PCS & PMA
Control & Status
Register Memory Map
S
Reset
Controller
S
Altera Transceiver
Reconfiguration
Controller
Offset Cancellation
Analog Settings
Avalon-MM PHY
Management
Read & Write
Control & Status
Registers
M
Avalon-MM master interface
M
S
Avalon-MM slave interface
S
PLL CDR
Rx Deserializer
Tx Serializer
Hard logic for Stratix V, variable for Stratix IV
Soft logic for Stratix IV and Stratix V