User guide

6–18 Chapter 6: PHY IP Core for PCI Express (PIPE)
Simulation Files and Example Testbench
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
For Stratix V devices, each channel and each TX PLL have separate dynamic
reconfiguration interfaces. The parameter editor provides informational messages on
the connectivity of these interfaces. Example 6–1 shows the messages for a 8-channel
PHY IP core for PCI Express (PIPE).
Although you must initially create a separate reconfiguration interface for each
channel and TX PLL in your design, when the Quartus II software compiles your
design, it reduces the number of reconfiguration interfaces by merging
reconfiguration interfaces. The synthesized design typically includes a
reconfiguration interface for three channels. Allowing the Quartus II software to
merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver
channels.
Table 6–13 describes the signals in the reconfiguration interface. This interface uses
the Avalon-MM PHY Management interface clock.
Simulation Files and Example Testbench
Refer to “Running a Simulation Testbench” on page 1–4 for a description of the
directories and files that the Quartus II software creates automatically when you
generate your PHY IP core for PCI Express.
f Refer to the Altera wiki for an example testbench that you can use as a starting point
in creating your own verification environment.
Example 6–1. Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 9 reconfiguration interfaces for connection to the external
reconfiguration controller.
Reconfiguration interface offsets 0-7 are connected to the transceiver channels.
Reconfiguration interface offset 8 is connected to the transmit PLL.
Table 6–13. Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr [<r>70-1:0] Sink
Reconfiguration signals from the Transceiver Reconfiguration
Controller. <r> grows linearly with the number of reconfiguration
interfaces.
reconfig_from_xcvr [<r>46-1:0] Source
Reconfiguration signals to the Transceiver Reconfiguration
Controller. <r> grows linearly with the number of reconfiguration
interfaces.