User guide

Chapter 7: Custom PHY IP Core 7–5
Parameter Settings
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 7–4 shows the resulting reset controller mode for various combinations of the
pma_rx_setlocktodata and pma_rx_set_locktoref registers. As Table 7–4 indicates,
setting either
pma_rx_setlocktodata or pma_rx_set_locktoref disables the automatic
reset controller.
Avalon data interfaces On/Off
When you turn this option On, the order of symbols is changed.
This option is typically required if you are planning to import your
Custom PHY IP core into a Qsys system.
Enable embedded reset control On/Off
When On, the automatic reset controller resets your design at
power up. When Off you can design you own reset logic using
tx_analogreset , rx_analogreset , tx_digitalreset ,
rx_digitalreset , and pll_powerdown which are top-level ports
of the Custom Transceiver PHY. You must turn this option Off to
implement your own reset controller.
By default, the CDR circuitry is in automatic lock mode whether you
use the embedded reset controller or design your own reset logic.
You can switch the CDR to manual mode by writing the
pma_rx_setlocktodata or pma_rx_set_locktoref registers
to 1. If either the
pma_rx_set_locktodata and
pma_rx_set_locktoref is set, the CDR automatic lock mode is
disabled as Table 7–4 illustrates. For more information about the
reset control and status registers, refer to Table 7–21 on
page 7–21.
For more information about reset in Stratix V devices, refer to
Transceiver Reset Control in Stratix V Devices in volume 3 of the
Stratix V Device Handbook.
Table 7–3. General Options (Part 3 of 3)
Name Value Description
Table 7–4. Reset Mode
rx_set_locktoref rx_set_locktodata CDR Lock Mode
1 0 Manual RX CDR locked to reference
X 1 Manual RX CDR locked to data
0 0 Automatic RX CDR